Measuring Dynamic
R
DS(on) Without a
Clamping Circuit
APPLICATION NOTE
D
4/5/6 Series MSO
Oscilloscope
VDS unclipped
SiC/GaN
G
device
ID
VDS clipped
S
Measuring Dynamic RDS(on) Without a Clamping Circuit
APPLICATION NOTE
Introduction
Dynamic on state resistance, RDS(on), is an important
parameter for designers working to understand the impact
of charge trapping in their power converter designs.
However, the body of knowledge around measurement
techniques is still relatively young. Traditional techniques
for measuring dynamic RDS(on) rely on diode clamping
circuits to allow oscilloscopes to measure drain to source
voltage with adequate resolution, without overdriving
the input of the scope. A new software clamping method,
introduced in Tektronix Wide Bandgap Double Pulse Testing
measurement software for the 4, 5 and 6 Series MSO
oscilloscopes, uses a unique double-probing technique that
eliminates the need for a clamping circuit.
What is Dynamic RDS(on)?
Dynamic RDS(on) is the average resistance between a
Figure 1. The RDS(on) waveform is the ratio of VDS to ID as they change during
FET’s drain and source terminals when it is turned on
the on state.
during switching. Drain-to-source resistance, RDS(on),
is an important parameter for any FET since it is a key
Challenges in Measuring
determinant of conduction loss and efficiency. RDS(on) is
computed as the ratio of the drain-to-source Voltage (VDS)
Dynamic RDS(on)
and the Drain Current (ID), and can be represented as a
To measure RDS(on), one must be able to accurately measure
function of time as:
VDS(t). The main challenge in measuring RDS(on) arises from
VDS(t)
the need to measure a small ON voltage within a high-
RDS(on)(t) =
ID(t)
amplitude switching signal. The amplitude of the switching
voltage, VDS(t), can be 800 V or more, depending on the
RDS(on) can then be represented as an average value of this
application. However, in the on-state, VDS(t) will be low, on
function during the on portion of a switching cycle.
the order of 10 V or less, as shown in Figure 2. In addition,
Dynamic RDS(on) occurs due to charge trapping phenomena
GaN and SiC FETs can switch with extremely high slew
in complex semiconductor structures. Researchers
rates. These factors result in significant measurement
studying GaN semiconductors are especially interested in
challenges:
dynamic RDS(on). GaN FETs can experience a phenomenon
• Capturing the VDS signal over its full range results in
known as current collapse, in which dynamic RDS(on)
poor digital resolution for VDS(on). The ADC quantization
increases. This can occur when electrons become trapped
error represents a large proportion of the signal. This
within the device structure in the off state, when a high
results in large quantization noise.
voltage is present between the drain and source. Although
less critical for SiC devices, designers may also be
• Simply increasing vertical sensitivity on the
interested in measuring dynamic RDS(on).
oscilloscope results in overdriving input amplifiers on
the measurement system.Unless corrected, this results
in measurement error during overdrive recovery.
• Fast slew rates introduce aberrations due to parasitic
inductance and capacitance. These take time to
settle out.
Since the switching voltage VDS can be high and may be
floating relative to ground, it is common to use high voltage
differential probes to measure the switching voltage.
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Measuring Dynamic RDS(on) Without a Clamping Circuit
APPLICATION NOTE
Differential probes help to avoid grounding issues which can
The new software clamping technique in WBT-DPT
reduce the accuracy of RDS(on) measurements. THDP Series
measurement automation software enables designers
differential probes are often on hand in power labs. For
to make quick measurements of dynamic RDS(on) with
these reasons, THDP Series probes have been tested for use
equipment they may already have on hand.
in this method and are recommended.
A New Oscilloscope-based
As noted, if one uses a low sensitivity (high V/div) to capture
the entire range of VDS, the voltage during the off state is
Approach to Clamping
acquired with low resolution since it represents just a small
Tektronix’ software clamping method eliminates the need
portion of the scope’s analog-to-digital converter (ADC)
for dedicated clamping circuitry. Instead, it relies on an
and the probe’s amplifier range. One possible approach is
oscilloscope with two high voltage differential probes
to acquire the low ON voltage at a high sensitivity (low V/div)
attached across the FET to measure drain-source voltage
in order to take full advantage of the differential probe and
(VDS). As shown in Figure 3, two instances of VDS voltage are
scope range. Unfortunately, acquiring a high amplitude
measured using two differential probes with each probe is
signal with high sensitivity will overdrive the amplifier in the
set to a different sensitivity.
differential probe, causing it to produce inaccurate data
during a short period of overdrive recovery.
D
4/5/6 Series MSO
Oscilloscope
VDS
Correct this as it
800 V
2nd ON
would have been
VDS unclipped
acquired with
SiC/GaN
G
10 V/div
device
ID
VDS clipped
VSCALE
100 V/div
10 V
0 V
100 A
ON region
ID
S
. One
Figure 3. Two high-voltage differential probes are used to measure VDS
0 A
probe is set to a high range (e.g. 1500 V) and high vertical scale (e.g. 100 V/div).
The other is set for a low range (e.g. 150 V) and lower vertical scale (e.g.
Figure 2. The high amplitude of VDS, along with the small ON-state voltage,
10 V/div).
makes it challenging to measure RDS(on). This new method enables high
sensitivity measurements with corrections.
• One differential probe captures the entire high to low
transition on VDS as the FET turns off.
Traditionally an external diode clamping circuit has been
used to eliminate the high-voltage portion of VDS(t). While
• The other differential probe captures only the RDS(on)
this approach can be effective, it has some drawbacks:
region at high sensitivity, providing high resolution
while the FET is turned on and VDS is small. This has the
• Introduces additional parasitic capacitance, inductance
effect of intentionally clipping the signal on VDS. Note
and resistance into the signal path
that this method is similar to clipping the signal using
• Introduces voltage offset associated with the RC time
a diode clamping circuit but requires the application of
constant of the resistor and parasitic capacitances
corrections to get good results.
of diodes.
• Voltage peaks increase with value of the resistance and
can be several times the clamping voltage.
• Adds additional cost to the test system
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Measuring Dynamic RDS(on) Without a Clamping Circuit
APPLICATION NOTE
Figure 4. The Drain-Source Voltage (VDS) is captured using a pair of THDP0200 High Voltage Differential Probes. One probe acquires the complete VDS vertical data
with an appropriate vertical scale. The other probe attached to VDS acquires the data at a more sensitive vertical scale, which results in a clipping warning on the
associated channel.
The WBG-DPT software combines the full-scale and
time” and is a common amplifier specification. The dynamic
high-sensitivity (but overdriven) VDS waveforms to derive
RDS(on) algorithm in the WBG-DPT application applies
a high-resolution composite waveform for the drain-to-
multiple techniques to mitigate the effects of:
source voltage in the on state. Normally, overdriving a
• Excessive quantization ADC noise at low sensitivities
differential probe or the front end of an oscilloscope is not
(high V/div)
recommended, since measurements can be of questionable
quality while the amplifier recovers from being driving
• Random noise
beyond its rails. This is referred to as “overdrive recovery
• Probe settling time, probe error and aberrations
• Overdrive recovery on clipped waveforms.
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Measuring Dynamic RDS(on) Without a Clamping Circuit
APPLICATION NOTE
Figure 5. A clipped reference waveform (R4) and full-scale waveform (R1) are combined through signal processing to generate a derived VDS(on) (M1) which uses
information from the full-scale VDS to correct the clipped VDS while maintaining the high-resolution information in the clipped waveform.
The effects of quantization error, settling time and overdrive recovery can be seen in Figure 5, Reference 4 which is
overdriven/clipped shows extended ringing and a recovery time to reach actual voltage value. Reference 1 is unclipped,
capturing the complete VDS voltage signal up to the bus voltage, but with clear quantization issues.
Using Signal Conditioning to Derive Low-Noise VDS(on)
In a typical Double Pulse Test (DPT), the switching device is
oscilloscopes typically have time constants around
initially turned on during the first pulse, allowing the current
10 µs, so a 50 µs settling time is generally adequate.
through the load inductor to increase linearly until it reaches
• First and second pulse width should at least be 10 µs so
the desired test level. The device is then turned off and
that the algorithm can ignore the initial ripple and focus
subsequently reactivated with a second pulse to evaluate its
on the actual RDS(on).
switching performance at the specified test current. RDS(on)
• Sufficient delay between bursts exists to allow the DUT
is measured during the second pulse.
to stabilize between double pulse tests.
The signal conditioning algorithm for VDS(on) assumes the
• The vertical scale of the clipped VDS waveform is
following conditions are met:
sensitive enough to provide adequate resolution, but
not so sensitive that the signal is underrepresented.
• Two turn-on cycles are executed in bursts, as in a
double pulse test. Information from the first pulse is
The WBG-DPT application’s PRESET function sets the scale
used to enhance the second pulse. A 50 µs gap between
automatically based on the specified VDS switching voltage.
first and second pulse is necessary so that any settling
These steps outline the high-level steps within the Dynamic
errors are the same for both turn-ons. Probes and
RDS(on) measurement algorithm.
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Measuring Dynamic RDS(on) Without a Clamping Circuit
APPLICATION NOTE
1.
Waveform averaging applied to multiple Double Pulse Tests
To reduce the impact of random noise on measurements, multiple double pulse tests may be performed and the resulting
waveforms averaged. The WBG-DPT RDS(on) measurement provides a control for this and defaults to eight waveform
averages per measurement.
2. Full-scale and Clipped VDS(on) segments are combined
Figure 6. Combining full-scale (Channel 2) and clipped (Channel 3).
This process uses information from the full-scale VDS(on)
up or down, of the full-scale signal. This difference is
and the clipped VDS(on) segments to construct a high-
applied linearly to the VDS-clipped samples in Window 1 as
resolution, derived VDS waveform.
a correction.
• This same “sliding window” process is applied to all
• The algorithm divides the on-segments of both the full-
windows before and after the reference window.
scale, VDS-full, and clipped, VDS-clipped, samples into n
horizontal windows each with k samples.
This correction maintains the high-resolution information in
the clipped samples by using the unclipped full-scale signal
• Mean values, AVG(VDS-full) and AVG(VDS-clipped ), of the
to generate low-frequency offset corrections. A composite
samples are determined for each window.
waveform with enhanced vertical resolution during
VDS
• The window with the smallest difference between
the ON time is the result. The derived VDS represents the
AVG(VDS-full) and AVG(VDS-clipped) is found. This
ON region as though the time domain waveform had been
window becomes the reference window, or Window 0.
acquired with lower vertical scale.
The average values here are AVG(VDS-full (0)) and
AVG(VDS-clipped(0)).
3. Turn-on 1 is subtracted from Turn-on 2 to remove
settling errors
• The difference between these two means is subtracted
from all samples in the clipped VDS window. This shifts
Within the composite VDS waveform any settling errors in
the high-resolution VDS-clipped samples to the same
the two voltage steps between VDS(off) and VDS(on) should
average level as the full-scale VDS-full signal.
be nearly identical in the first and second pulses, since
the step size is approximately the same for both pulses.
• The algorithm then moves on to the next window,
This assumes that the time between the two turn-ons
for example Window 1. The difference between
is adequate to allow the measurement system to settle
AVG(VDS-full(1)), and previous window, AVG(VDS-full(0), is
between cycles.
found. Note that this difference represents the trend,
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Measuring Dynamic RDS(on) Without a Clamping Circuit
APPLICATION NOTE
Thus, to remove consistent settling errors from the derived VDS, samples from the first VDS(on) segment are subtracted
from samples from the second VDS(on) segment. This removes both the settling error, as well as any VDS(on) common to both
pulses. The remaining voltage in the second pulse will be due to the higher current flowing through RDS(on) in the second
pulse. Id from the first on-cycle is subtracted from Id from the second cycle, to isolate the incremental current flowing
through RDS(on).
Once the incremental voltage and current from the second off-cycle are known, the samples for RDS(on) are calculated using
Ohm’s Law. These samples are displayed and can be used to determine measurements such as average RDS(on) over the
cycle. Note that due to the signal processing outlined above, only the RDS(on) associated with the second off-cycle is valid and
displayed.
Figure 7. A 5 Series B MSO equipped with WBG-DPT Double Pulse Testing Analysis, measuring dynamic
Limitations on this New RDS(on)
Performing Dynamic RDS(on)
Measurement Technique
Measurements Using Software
As with any procedure for measuring dynamic RDS(on), care
Clamping Technique
must be taken when using this new method. As noted above,
Based on the theory of dynamic RDS(on) measurements
10 µs pulse widths and a 50 µs gap between pulses are
and the double-probing technique outlined in the previous
recommended. The clipped waveform has the restriction
sections, we will now cover the application of the RDS(on)
on the vertical scale. The algorithm has been tested using
measurement using this new approach, including the test
Tektronix THDP Series High Voltage Differential Probes but
setup, procedure, and interpretation of results.
has not been tested using other probes. The method is not
suitable for measuring dynamic RDS(on) of less than 10 mΩ.
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Measuring Dynamic RDS(on) Without a Clamping Circuit
APPLICATION NOTE
Test Setup
The test setup for performing dynamic RDS(on)
• AFG 31000 Series function generator
measurements is shown in Figure 8 and Figure 9.The
• TRCP, TCP0030A or TCP0150 or CVR with TICP Current
system comprises:
D
Probe or for measuring I
•
4, 5 or 6 Series B MSO oscilloscope
• TPP1000 for low side VGS
• WBG-DPT Double Pulse Testing software license
• Power Supply to source VDD
• THDP0100 or THDP0200: 2 each for measuring clipped
• SiC or GaN test board as DUT
VDS and full scale VDS signals
D
AFG31000
G
S
DC Power Supply
+
4/5/6 Series B MSO
-
D
G
Isolated
VGS
Gate Drive
VGS
S
Circuit
ID
TPP1000
Passive Voltage Probe
THDP0100/THDP0200
Clipped VDS
THDP0100/THDP0200
Full Scale VDS
TRCP or TCP Current Probe
or TCP Series and CVR
Figure 8. A test setup for measuring the dynamic RDS(on) of a low-side FET. Note that two high-voltage differential probes are applied across the drain and source
terminals of the FET.
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Measuring Dynamic RDS(on) Without a Clamping Circuit
APPLICATION NOTE
Figure 9. Dynamic RDS(on) test setup in a lab.
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Measuring Dynamic RDS(on) Without a Clamping Circuit
APPLICATION NOTE
Dynamic RDS(on) Measurement Steps
On the oscilloscope, the RDS(on) measurement is added from
the WBG-DPT Add Measurements Panel (Figure 10). The
settings for the dynamic RDS(on) measurement are opened
by double-clicking on the measurement badge. This opens
the panel shown in Figure 11. The five steps for setting up
the measurement are shown in the panel.
Figure 11. The RDS(on) measurement panel outlines the steps for making the
measurement.
1.
First, the Configure panel is opened and the channel
Figure 10. In the WBG-DPT application, the RDS(on) measurement is one of
assignments for Vds full scale, Vds clipped, Id and
several switching parameter measurements.
Vgs are made.
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Measuring Dynamic RDS(on) Without a Clamping Circuit
APPLICATION NOTE
3. The nominal maximum values of Vds, Id and Vgs are
entered.Clicking on Power Preset uses this information
to configure the oscilloscope’s vertical scales,
horizontal scale, trigger and acquisition settings.
Figure 14. Nominal maximums are used to set scaling.
4. The current and voltage probes are deskewed using
the special software deskew process built into the
Figure 12. Assigning oscilloscope input channels to voltage and
current sources.
WBG-DPT software. Clicking on the WBG Deskew
button acquires voltage and current waveforms, and
2. Next, the LAN-connected AFG31000 is configured to
automatically adjust channel-to-channel delay to
generate the double pulse test signal.The first and
compensate for different probe delays.
second pulses should at least be 10 µs wide with a 50 µs
gap between first and second pulse, as explained in
“Signal Conditioning to Derive Low-Noise VDS(on)”, above.
Figure 15. WBG Deskew is used to automatically remove timing skew
between probes.
Figure 13. Setting up the double pulse stimulus from the signal generator, with
10 µs pulses separated by a 50 µs gap.
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Measuring Dynamic RDS(on) Without a Clamping Circuit
APPLICATION NOTE
Figure 16. After clicking OK in the RDS(on) panel the oscilloscope is ready to acquire waveforms. The measurement badge now includes a button to initiate the Gate
Stimulus. During the test it shows the number of complete acquisitions and after the test it shows the number of completed acquisitions and after the test it sows
the average dynamic RDS(on).
5. The OK button in the RDS(on) panel is clicked and the oscilloscope is ready to make the measurement.A Gate Stimulus
button appears in the measurement badge, as shown in Figure 16. Once this button is clicked, the measurement badge
shows the number of completed acquisitions, followed by the final average RDS(on).
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Measuring Dynamic RDS(on) Without a Clamping Circuit
APPLICATION NOTE
Figure 17. An RDS(on) measurement result on the 5 Series B MSO.
Measurement Results
As shown in Figure 17, after initiating the RDS(on) measurement from the measurement panel, the oscilloscope will acquire
the VDS (clipped and un-clipped) and ID signals. The RDS(on) measurement algorithm uses the two VDS signals to calculate a
high-resolution, composite VDS signal during the second turn-on stage. This is shown in Figure 18.The composite VDS signal is
divided by ID to find RDS(on) during the second turn on stage.
Figure 18. Derived VDS and RDS(on) waveform detail from the RDS(on) measurement.
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Measuring Dynamic RDS(on) Without a Clamping Circuit
APPLICATION NOTE
The software method has been shown to correlate well with clamping circuits. While there will be variations between
individual power devices, this method has been shown to provide a general indication of how RDS(on) changes with current
and temperature. An example set of results for the software method and traditional hardware clamping is shown in Figure 19
for comparison.
Figure 19. Scatter plot of the RDS(on) measurement of a Qorvo MOSFET, using the software clamping method (left) and an external clamping circuit (right).
Conclusion
References
This oscilloscope-based clamping approach can provide
1.
L. Ren, Q. Shen and C. Gong, “A voltage clamp circuit
a way to compare measured results to expected results.
for the real-time measurement of the on-state voltage
It should not be used for device characterization, but can
of power transistors,” 2016 IEEE Energy Conversion
guide designers as they evaluate devices and designs. This
Congress and Exposition (ECCE), Milwaukee, WI, USA,
signal-processing approach provides useful measurements
2016, pp. 1-7, doi: 10.1109/ECCE.2016.7854807. A voltage
of dynamic RDS(on) in WBG devices, facilitating better
clamp circuit for the real-time measurement of the
optimization of switching efficiency and thermal
on-state voltage of power transistors | IEEE Conference
management strategies. This method simplifies the test
Publication | IEEE Xplore
setup while providing an accurate representation of device
2. M. Šír and I. Feňo, “Measurement Method for the Dynamic
behavior under high frequency switching conditions.
On-State Resistance of GaN Semiconductors,” 2018
2nd European Conference on Electrical Engineering
and Computer Science (EECS), Bern, Switzerland, 2018,
pp. 543-546, doi: 10.1109/EECS.2018.00106. https://
ieeexplore.ieee.org/document/8910040
3. A. N. Rahman, M. -Y. Li, M. Tampubolon and H. -J.
Chiu, “High Resolution Dynamic RDS(on) Measurement
of GaNFET using Active VDS(on) Measurement Clamp
Circuit,” 2019 IEEE Workshop on Wide Bandgap
Power Devices and Applications in Asia (WiPDA
Asia), Taipei, Taiwan, 2019, pp. 1-4, doi: 10.1109/
WiPDAAsia.2019.8760329. High Resolution Dynamic
RDS(on) Measurement of GaNFET using Active
VDS(on) Measurement Clamp Circuit | IEEE Conference
Publication | IEEE Xplore
14 | WWW.TEK.COM
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