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Testing High Speed Serial Standards over Type-C


Consumer Standards over Type-C

for next gen USB, DisplayPort, and Thunderbolt

Testing High Speed Serial Standards over Type-C

The Type-C connector provides consolidation of High Speed Serial consumer standards like USB 3.1, DisplayPort 1.4, and Thunderbolt, providing low power, low cost, higher speed and higher resolution displays. This translates to new design challenges due to the need for emphasis on the transmitter side and equalization on the receiver side making it difficult to keep design costs low while maintaining optimal electrical margins on your products.

Get to compliance faster

Compliance level testing time is critical and the sheer number of measurements required make automation important. You get fast push-button pass/fail compliance information with TekExpress based test automation software (for example 3X faster than a competitor's software for DisplayPort).


Build confidence on the margin of devices

To characterize the designs, there is a need to perform vertical and horizontal jitter decomposition to understand device behaviors. To build confidence on the margin of devices, you need the ability to render an eye diagram with extrapolation and analyze the channel effect on the signal at the far end using different channel models. Go beyond simple pass/fail compliance and get in-depth debugging insight (jitter, noise, eye height/width, visualization plots, using BER contours) into compliance failures with Tektronix DPOJET. Pick the optimal channel needed for your designs with Tektronix SDLA that supports different channel models to simulate the effect on signal. Analyze waveforms in offline mode and collaborate with your global teams to reduce your time to market.


BER contour for USB 3.1 Gen 2 at 10Gbps extrapolated at 1E-12.

Avoid expensive overdesigning


USB receiver jitter tolerance margin test with single-click operation.

Debugging DUT loopback issues are difficult because typical BERTs don't support protocol handshaking and logging. The protocol sequencer in the Tektronix BSX series BERT solution addresses the challenge of debugging loopback issues.

Receivers can be expensive to design and overdesigning margins on the receiver can be even more expensive. It’s a tricky affair to ensure that the receiver has sufficient margin to pass compliance, be competitive, while maintaining the cost of the parts. Margin analysis tools on the BERTScope help you understand the margin available on early designs and make the right kind of trade off decisions before you finalize your designs.


When the DUT is in loopback, all states and sub-states colors will be ‘green’. If not the failed states turn ‘red’ and are clickable to receive a diagnostic message.

Facing challenges in other wired communication applications?

Reference our configuration guide to find standard configurations, options, and other support for planning purposes. This guide will be updated as new configurations are created.