High Speed Serial Communications

High-speed digital standards are quickly evolving to support the performance demands of our data driven world. Next generation serial standards and data communication requirements are bringing new test challenges, pushing the limits of today’s compliance and debug tools. From design and simulation, analysis, debug, and compliance testing, Tektronix provides advanced, automated measurement solutions to optimize performance, speed up validation cycles and accelerate time-to-market.

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Accelerate PCIe, SAS, SATA Test and Debug

Keeping pace with the next generation of data rates and storage standards requires end-to-end solutions that can scale to 32Gb/s while providing current-gen capabilities.

Discover how to accelerate your design testing and debug.

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Consumer Standards over Type-C

The Type-C connector provides consolidation of consumer standards USB 3.1, DisplayPort 1.4, and Thunderbolt. This translates to new design challenges making it difficult to keep design costs low while maintaining optimal electrical margins on your products.

Discover how to tackle these new challenges.

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e-Guide to High Speed Interface Standards

This FREE e-Guide will help you learn more about design challenges for testing PCIe 4.0, SAS, SuperSpeed USB, and DDR4 standards. You get quick access to technical resources that will help you understand design challenges and pick the right solution for your test needs.

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Library

Title
MIPI Debug and Conformance Testing Challenges and Solutions
Characterizing an SFP+ Transceiver at the 16G Fibre Channel Rate Figure 1. An example Fibre Channel topology. Abstract The Fibre Channel standard is evolving to include the next generation "16G" …
PCI Express® Transmitter PLL Testing — A Comparison of Methods Abstract The electrical compliance test specification drafted by PCISIG requires testing loop response of the Phase Locked Loop (PLL) used in add-in cards to generate a local …
PCIe Gen 5 Tx Tech Brief Background With the expected dramatic rise in the number of internetconnected devices and associated high bandwidth requirements of 5G and Internet of Things (IoT), data center …
High Speed Interface Standards This e-Guide will help you learn more about design challenges for testing PCIe 4.0, SAS, SuperSpeed USB, and DDR4 standards. Within the pages of the eGuide you will also get quick access to technical …
PCI Express Gen5 Automated Multi-Lane Testing Introduction Comprehensive characterization of high-speed links such as PCI Express® require performing measurements of the Transmitter (Tx) and Receiver (Rx) across multiple …
Fast+ Efficient Solutions for DVI Conformance Measurement Challenges Tektronix Supports DVI Conformance Testing with TDSDVI Expert Application software If you've got a DVI product in the works, you need …
Probing Tips for High Performance Design and Measurement FIGURE 1. Probe loading is dependent upon the input impedance of the probe and the sensitivity of the circuit to this impedance. When …
Remote Head Acquisition Improves High Speed Serial Measurement With serial data rates continuing to climb, it's more important than ever to minimize the impact of the measurement system's internal noise on the measured signal. As output voltages …

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PCIe Gen5 to Gen6 and Comparison to Electrical Ethernet Watch as David Bouse explains the evolution of PCI Express from Gen5 to Gen6. Then hear from Pavel Zivny as he and David discuss PAM4 signaling in PCIe and how it compares with PAM4 as applied in …
How to Address Your Toughest Serial Bus Design Challenges with EDA and Measurement Correlation This Tektronix webinar will teach engineers how to use modeling tools to correlate simulations with high-speed physical layer measurements on Serial Bus Standards using the DPO/MSO70000 Series …
DDR5 Test Challenges Webinar Learn how you can address five of the thorniest measurement challenges associated with the new DDR5 standard. Get an update on the DDR5 Rx/Tx compliance test and insight in the latest characterization …
PCI Express Gen 4 and Gen 5 Transmitter and Receiver Validation PCI Express I/O bandwidth has doubled every 3 years on average thereby leading to an increased demand for this full duplex high speed bus architecture. As the industry begins deploying the 5.0 …
MIPI C-PHY D-PHY Webinar MIPI alliance standards have been driving the adoption of newer features and higher data rates for emerging mobile applications. Oscilloscope-based protocol layer validation enables isolating …
Demystify MIPI D-PHY and C-PHY Transmitter and Receiver Physical Layer Test During this webinar, you'll gain an understanding of MIPI test challenges for both MIPI high-speed physical layers. You'll also get useful tips and technical insights into characterizing and …
Thunderbolt Compliance Test Setup Webinar View our webinar, Choosing the Best Test Setup for Thunderbolt™️ Compliance Testing, and learn which test setup is best suited for your Thunderbolt 3 and Thunderbolt 4 design.
USB4 Webinar View our USB4 Compliance and Characterization Test webinar to learn how you can address the measurement challenges associated with the new USB4 standard.
PCIe Gen6 PAM4 Signaling Prepare for the next PCI Express inflection point by viewing this discussion of validation requirements for PCI Express Gen6. We review newly introduced transmitter measurements including SNDR and …
PCI Express Gen 5 Reference Clock Webinar This webinar presents an overview of reference clock jitter requirements as they have evolved and offers techniques for making these low femtosecond measurements using a real time oscilloscope.
DDR5 Memory Characterization While they promise to provide datacenters with large amounts of data at faster speeds and lower power consumption, DDR5 memory devices have unique test challenges. Learn about characterization and …
PCI Express Gen 5 Update Webinar Cloud-based computing power, storage capacity, and network bandwidth have led to the development of the PCI Express 5.0 specification for 32.0 GT/s. This webinar starts with an overview of 5.0 …