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Where Are We Going after PCIe 6?

The physical layer of PCIe Express® has rapidly evolved from Gen 4.0 to Gen 5.0 and finally to Gen 6.0 with a 6.0 spec that describes everything that's necessary to develop silicon. We’ve gone from 16 to 32 and for Gen 6.0 up to 64 GT/s (Giga-transfers per second). And for the first time, we've gone to PAM4 multi-level signaling that allows us to encode two bits of information into a single unit interval. The result is a doubling of the data rate we had for Gen 5.0..

At this year’s Tektronix Innovation Forum I had the opportunity to take part in a panel discussion with two industry experts: Madhumita Sanyal from Synopsys and Hiroshi Goto from Anritsu. We discussed the challenges with the latest PCIe release and what may be in store for 7.0. The development and design of PCIe Express 6.0 is still unfolding and maturing, including the form factor standards, the test specs, etc. Yet, the PCI-SIG® has already announced, and work has already started on Gen 7.0 – we're expecting a base spec by 2025. We're anticipating 128 giga-transfers per second and PAM4 signaling just like we saw for Gen 6.0 as well.


Data Rate
PCIe 4.0
PCIe 5.0
PCIe 6.0
16 GT/s
32 GT/s
64 GT/s (PAM4)
Add-in Card Loss
8dB @ 8Ghz
9.5dB @ 16GHz
8.5dB @ 16GHz
Full Channel Loss
- (27 to 30) dB @ 8GHz
- (34 to 37) dB @ 16GHz
- (30 to 33) dB @ 16GHz
Reference CTLE
2 Poles; 1 Zero
4 Poles; 2 Zero
6 Poles; 3 Zero
Reference DFE
Eye Width (Rx Test)
18.75 ps
9.375 ps
3.125 ps (top eye)
Eye Height (Rx Test)
15 mV
15 mV
6 mV (top eye)

As Madhumita stated:

“It’s a really interesting era now, going from 64 GT/s to 128 GT/s. So, it's basically the need for 1.6 terabyte ethernet with 16 lanes times 128, 2 terabytes per second, unidirectional bandwidth. That's the requirement coming from the ethernet world. And PAM4 is retained, and Nyquist is now 32 gigabytes, but it needs to be backward compatible with all previous generations.

“I think it will still use the Flits, and who knows which FEC may be stronger? FEC is required like ethernet LAN Reed Solomon or maybe light FEC will still do and increase the bit rate spec. But of course, it's likely to be very, very evolutionary with respect to the protocol itself. I believe the electricals will be very, very tough, depending on how PCI-SIG defines the channels. Likely, we'll need new boards, connectors, cables. Definitely some new challenges for the SERDES transmitter and receiver architecture lie ahead.”

Hiroshi Goto added:

“The package has increased so how much is the channel loss? And from Gen 5.0 to Gen 6.0, from 32 GT/s to 64 GT/s – the skew between P and N, positive or negative, is very, very critical now. The one-millimeter difference of the cable brings five picoseconds of mismatch. So, the P and N skew mismatch is also very critical.

“There has been a lot of work looking into how to maintain the backwards compatibility with the card electromechanical (CEM) connector. I think that's something to keep an eye on and see. Can we still achieve that backwards compatibility? Will we have to look at alternative sorts of connections for going from the host to the endpoint?”

Subsequent to the panel discussion, Tektronix attended the June 13-14, 2023, PCI-SIG Developers Conference in Santa Clara where PCI-SIG announced the PCI Express (PCIe) 7.0 specification has reached version 0.3.

At that event, Synopsys took what they called a “sneak peek” at the upcoming PCIe 7.0 data rate of 128 GT/s in a demonstration with Tektronix. In a demonstration, a Synopsys evaluation board was shown sending a PRBS pattern to a Tektronix DPO70000SX oscilloscope. All three 128 GT/s PAM4 eyes were open with good linearity among them, low jitter and good Ratio Level Mismatch (RLM). 

PCI Express 128GT/s PAM4 Eye

A Successful 128GT/s PAM4 Eye

A second demonstration by Anritsu highlighted their MP1900A BERT working with a Tektronix DPO70000SX real time oscilloscope and the Synopsys PCIe 6.0 PHY & Controller IP in an end-to-end system showcasing pre-FEC and post-FEC BER. In this demonstration, a 33db stressed eye pattern having been calibrated by the Tektronix oscilloscope is sent by the Anritsu BERT, acting as a host, to the Synopsys end-to-end solution with PHY end controller. The receiver equalizes the stressed pattern and loops the signal back through the controller to the PHY transmitter which then returns the signal to the Anritsu BERT. Link training for all generations up including Gen 6 phases 1-3 were completed and tests passed.

PCIe 6 Receiver Link Training Compliance Test System

Learn more about Tektronix solutions for PCIe up to and including Gen 6.0 online. The panel discussion was just one of nearly 20 technical sessions at the Tektronix Innovation Forum 2023. Get access to all of them by registering for the event.

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