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PCI Express

Accelerate the analysis, validation, and pre-compliance testing of your PCIe design with test solutions from Tektronix.

With instruments and analysis software for both Transmitter and Receiver testing our solutions provide the ability to perform in-depth analysis, compliance testing, and debug for both current and next generation PCIe specifications (Standards Gen 1, 2, 3 and now PCIe 4.0).

Library

Title
Tektronix helps PMTC with compliance tests on high-speed buses
Solution SummaryChallengeTo enable one of Europe's leading multimedia test houses carry out compliance testing on high-speed serial buses including USB2, Serial ATA and PCIExpress.SolutionA suite of …
PCI Express® Transmitter PLL Testing — A Comparison of Methods
There are several methods of measuring PLL loop response, based on the type of test instrumentation used. As expected, the various methods trade off test accuracy, test speed (throughput), ease of …
Logic Analyzer Fundamentals
Like so many electronic test and measurement tools, a logic analyzer is a solution to a particular class of problems. It is a versatile tool that can help you with digital hardware debug, design …
Understanding and Characterizing Timing Jitter Primer
Timing jitter is the unwelcome companion of all electrical systems that use voltage transitions to represent timing information. Historically, electrical systems have lessened the ill effects of …
Triggering Fundamentals With Pinpoint® Triggering and Event Search & Mark for DPO7000
This document discusses the fundamentals of triggering and how Pinpoint triggering and Search and Mark takes triggering in real-time oscilloscopes to new levels of productivity.
The Basics of Serial Data Compliance and Validation Measurements
High-speed serial bus architectures are the new norm in today’s high-performance designs. While parallel bus standards are undergoing some changes, serial buses are established across multiple markets …
Overcoming PCI-Express Physical Layer Challenges
This paper will present how the Tektronix Logic Protocol Analyzer is used to overcome these challenges using powerful triggering and multiple data views.
Understanding the Transition to Gen4 Enterprise & Datacenter I/O Standards
This whitepaper provides important information about adaptive equalization and link training, the impact of forward error correction (FEC) on compliance testing, debugging protocol handshaking and …
Advanced Serdes Debug with a BERT
Learn simple strategies to pinpoint bit errors to the exact bit position and timing with powerful Error Location Analysis and a BERT.
Hunting PCIE Flow Control Bugs
This white paper describes in detail the use of the Bird's Eye View (BEV), a completely new visualization, to investigate flow control. Not only does the BEV provide a full-acquisition view of the …
Overcoming Receiver Test Challenges in Gen4 I/O Applications
This new application note provides vital information on performing compliance and diagnostic tests for Gen4 enterprise receivers with Bit Error Rate Testers.  
Timing Error Debugging
New Designs, New HeadachesNew digital devices have become progressively more powerful by incorporating high-speed buses, subsystems, and logic families. They have also become more complex, more …
Time Domain Methods for Measuring Crosstalk for PCB Quality Verification Application Note
This application note discusses the elements of crosstalk and demonstrates how you can measure crosstalk on a single-layer PCB using the TDS8200 Series Sampling Oscilloscope or the CSA8200 Series …
Debug physical layer and link training issues quickly for standards running up to 32 Gb/s. Move from complexity to confidence.
2m 12s
The MSO/DPO70000 Series oscilloscope delivers exceptional signal acquisition performance and analysis capability. Discover your real signals and capture more signal details with the industry's …
5m 50s
In this video we look at a topic that is becoming increasingly important in the high-speed serial industry—how to perform embedded measurements at the IC or PCB level using probes.
4m 14s
Title
Understanding Differences between PCI Express 4050 and IEEE High Speed Electrical Specifications
Our Tektronix domain experts, Dan Froelich and Pavel Zivny, contrast the methodologies of the PCI Express 4.0/5.0 and IEEE 26 GBd NRZ/PAM4 electrical specifications and engage in a lively discussion …
Overcoming Challenges in PCI Express Compliance Testing
Learn the keys to debugging, verifying design and performing interoperability testing for PCI Express revisions 3.0 and 4.0.
Getting to PCI Express Compliance Faster
As design margins shrink, accurate and standard-specific measurement is key to debugging, verifying design and performing interoperability testing when designing PCIe devices. Having confidence in …
Addressing PCIe Gen1-5 Test and Debug Challenges with Confidence
Learn how to address the test and measurement challenges posed by PCIE Gen1-5 for both base silicon testing and CEM compliance testing. Gain insights and solutions for automation, validation, and …
Maximizing Margins for 4th Gen High Speed Serial Standards
As data rates increase, the effect of cables and fixtures become a larger part of the overall measurement result.  Cable and fixture effects can significantly reduce margins and thereby lead to …
Title
Methods of Implementation (MOI) for Verification+ Debug and Characterization
This document covers the Method of Implementation (MOI) for DPOJet measurements provided in the DPO70000 Option PCE, Option PCE3, and Option PCE4 solutions packages.
PCI Express 3.0 Card Transmitter Test MOI
This document covers the Method of Implementation (MOI) for PCI Express 3.0 CEM and U.2 card transmitter testing, using DPO70000 Series Oscilloscopes.
PCI Express 3.0 System Transmitter Test MOI
This document covers the Method of Implementation (MOI) for PCI Express 3.0 CEM and U.2 System transmitter testing, using DPO70000 Series Oscilloscopes.
PCI Express 3.0 De-embedding Method of Implementation Version 1.0
This document will provide a step-by-step procedure for extracting the Sparameters from the test channel of the PCI Express Gen 3 so it can be used for the purpose of removing the effects from the …
PCIe Gen 4.0 Rx & Link Equalization Test Procedure MOI
This document cover the Method of Implementation (MOI) for PCIe Gen 4.0 Rx and Link Equalization Test Procedures.
PCI Express 3.0 Receiver Test MOI for CEM Spec
This document covers the Method of Implementation (MOI) for PCI Express 3.0 CEM receiver testing, using BERTScope instruments. The document includes a step-by-step description of required hardware …
PCI Express 3.0 PLL Test MOI for Add-In Cards
This document covers the Method of Implementation (MOI) for PCI Express 3.0 Phase-Lock-Loop (PLL) testing for Add-In Cards (AIC) using BERTScope CR125A, CR175A, or CR286A Clock Recovery instruments …
PCIe Gen 4.0 TX CEM Test Procedure MOI
This document cover the Method of Implementation (MOI) for PCIe Gen 4.0 TX CEM Test Procedures.
PCIe Gen 4.0 CEM Add-in Card PLL Bandwidth Test Procedure MOI
This document cover the Method of Implementation (MOI) for PCIe Gen 4.0 CEM Add-in Card PLL Bandwidth Test Procedures.
PCI Express 3.0 Receiver Test MOI for BASE Spec
This document covers the Method of Implementation (MOI) for PCI Express 3.0 BASE receiver testing, using BERTScope instruments.
PCIe Gen 3.0 Link Equalization System and Add-in Card Test Procedure
Tektronix PCI Express Gen3 Link EQ test MOI. This document cover Link EQ testing for both System DUT and Add-In Card.
PCIe Gen3 (8GT/s) Receiver Jitter Tolerance Test MOI
This document covers the Method of Implementation (MOI) for PCIe Gen3 (8GT/s) Receiver Jitter Tolerance Test (Add-In Card and System) using Tektronix BSX Series BERTScope Bit Error Tester and …