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If you were unable to connect with us at DesignCon 2025, we invite you to learn more about our latest innovations in testing for compliance, power, and memory.

Download our show flyer, and feel free to schedule a personal meeting to discuss your specific application.

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Explore our Showcased Solutions

Automate Test at 64 GT/s for PCI Express 6.0 CEM Tx & Rx

Automate Test at 64 GT/s for PCI Express 6.0 CEM Tx & Rx

  • Enable upcoming spec release for 64.0 GT/s data transfer rate for faster processing to meet rapidly growing AI/ML needs.
  • Simplify complicated calibration and measurement of PAM-4 signaling with the Tek DPO70000SX oscilloscope’s wizard-based user interface automated test solution.
  • Test full compliance with backward compatibility to PCIe Gen 5.0, 4.0, and 3.0, Base and CEM.
  • Streamline compliance to debugging with Tektronix PAMJET/DPOJET toolsets.

Explore Pathfinding of 128 GT/s Measurements for PCIe 7.0 Base Specification

  • Analyze signal integrity of PAM-4 signaling at 128 GT/s, measurements of eye diagram, signal-to-noise distortion ratio (SNDR), and ratio level mismatch (RLM).
  • Characterize and compensate noise of measurement system for improved measurement accuracy.
  • Easily analyze to add reference receiver equalization and channel embed/de-embed.
128 GT/s Measurements for PCIe 7.0 Base Specification
USB4v2 Validation at 40 Gb/s

Streamline USB4v2 Validation at 40 Gb/s

  • Acquire and analyze in parallel improving speed and scope utilization.
  • Enhance accuracy through low intrinsic jitter.
  • Leverage latest industry-standard disaggregated architecture.
  • Enable advanced data management with results/reports repository, dashboard, waveform/plot display and download.
  • Analyze compliance failures with in-house debugging tool.

Empower Engineers with a Unified DDR5 DRAM Tx/Rx Test Workflow

  • Streamline testing processes by offering a cohesive experience with a unified Tx/Rx workflow.
  • Enable precise troubleshooting and quick issue resolution with flexible debugging capabilities.
  • Achieve greater flexibility and control over the testing process with customizable test plans.
  • Gain in-depth insights for accurate testing and validations with a wide range of advanced analysis options.
Unified DDR5 DRAM Tx/Rx Test Workflow
Power & Signal Integrity for GenAI Data Centers

Optimize Power & Signal Integrity for GenAI Data Centers

Achieve Energy Efficiency with Improved PI/SI Measurements

  • Evaluate ripple, transient characteristics, power supply sequencing, amplitude, jitter, eye and power supply noise.
  • NEW! Characterize power supply induced jitter (PSIJ).
  • Save time with one-click power rail measurements.
  • Gain insight into your power delivery network’s (PDN) impedance and power quality.
  • Ensure energy-efficient and reliable data center designs with a complete power integrity solution.

Scale High-Power Battery Testing

Adapt to Any Power Test Application with Flexible Platforms

  • Easily test multiple high-power battery modules simultaneously using multiple channels for load or power source.
  • Access a full range of voltage test parameters from low to high with a single device.
  • Characterize batteries at >1 kHz programming and measurement speeds.
  • Pre-charge, polarity check and external contactor control.
Scale High-Power Battery Testing
AI/HPC Interconnects

Enable Networking for AI/HPC Interconnects

Accurately Test 800G PHY Transmitter Conformance

  • Analyze signal integrity of PAM-4 signaling at 112 Gb/s, measurements of eye diagram, signal-to-noise distortion ratio (SNDR), and Jitter (J3u, Jrms, EOJ).
  • Quickly recover a clock on a PAM-4 signal; no external trigger source or hardware clock recovery required.
  • Achieve accurate results with best-in-class scope noise compensation.
  • Customizable software equalization for CTLE, FFE, DFE.

Tektronix Presentations

Date Presentation Time Location
Wednesday, January 29 Multiple Pulses-Based Decision Feedback Equalizer (MPDFE) for PAM4 11:15 AM - 12:00 PM PST Ballroom F Track 12
Thursday, January 30 The Expanded Role of SI/PI in Next Gen AI Data Center Development 11:15 AM - 12:00 PM PST Chiphead Theater
Thursday, January 30 200Gbps Lanes Equalization Methods & Required Fixture Bandwidth,
S-parameter Bandwidth & Acquired Signal Bandwidth		 12:15 AM – 1:00 PM PST Ballroom C Track 8
Thursday, January 30 Arbitrary Waveform Generator Assisted Digitalization of Physical Channels
with Fractional Sampling Rate for SerDes High-Speed Evaluation		 12:35 PM - 12:45 PM PST Chiphead Theater

Don’t forget to schedule a personal meeting to discuss your specific application. We look forward to seeing you there.

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