BSA Series BERTScope® Bit Error Rate Tester
Perform bit error ratio detection more quickly, accurately and thoroughly by bridging eye diagram analysis with BER pattern generation. The BERTScope Bit Error Rate Tester Series enables you to easily isolate problematic bit and pattern sequences, then analyze further with seven types of advanced error analysis that deliver unprecedented statistical measurement depth.
- Features and Benefits
- Software Packages
- Technical Documents
- Selection Guides
|Pattern Generation and Error Analysis, highspeed BER Measurements up to 28.6 Gb/sec.||The combination of impairment modulation, signal generation and analysis in one instrument enables receiver BER compliance testing for today's 3rd Generation Serial and 100G standards like; IEEE802.3ba, OIF-CEI and 32GFC communications standards.|
|Integrated Stress Generator for stressed eye sensitivity (SRS) and jitter tolerance compliance testing.||A test signal's data rate, applied stress, and data pattern can be changed on the fly, independent of each other; enabling a diverse set of signal variations for testing chipset/system sensitivity.|
|Integrated, BER correlated eye diagram analysis with pass/fail masks for PCI Express, USB, SATA and other communications standards.||Enhances the debug experience unlike other BERT's by providing a familiar eye diagram of the test results to compare against a standards specific mask.|
|Error Location and BER contour analysis on PRBS 31 and other digital signals up to 28.6 Gb/sec.||Provides a quick understanding of signal integrity in terms of BER. Error location provides detailed BER pattern sensitivities to speed up identification of deterministic vs. random BER errors.|
|Optional Jitter Map provides fast jitter decomposition, accurate stress calibration at the DUT input.||Fast, effective method for determining long pattern PRBS31 jitter composition with triangulation. Graphical representation makes jitter analysis more thorough, yet simpler to follow.|
|Optional Digital Pre-emphasis Processor provides user controlled pre-emphasis on pattern generator supplied data.||Enables testing with compliant signals for standards like OIF-CEI3.0, Infiniband EDR, PCI Express, 10GBASE-KR, SATA, 40GBASE-KR4, 100GBASE-CAUI.|
|Optional Clock Recovery Units provide clock recovery up to 28.6 Gb/s.||Enables compliant testing and accurate Eye Pattern Analysis for high-speed serial and communication system standards.|
|BSA12500ISI||Differential ISI Board|
|BSARACK||BSA-Rack Mount Kits, SAFETY CONTROLLED|
|PMCABLE1M||Precision Phase Matched Cable Pair, 1m|
|SMAPOWERDIV||SMA Power Dividers|
|BERTScope® Bit Error Rate Testers Jitter Map “Under the Hood”|
A New Methodology for Jitter Separation
|Bridging the Gap Between BER and Eye Diagrams — A BER Contour Tutorial|
Introduction to the BER Contour measurement.
|Clock Recovery Primer, Part 1|
Look at clock recovery from a practical point of view, Part 1.
|Clock Recovery Primer, Part 2|
Look at clock recovery from a practical point of view, Part 2.
|Comparing Jitter Using a BERTScope® Bit Error Rate Testing|
Comparison of DCD and F/2 Jitter.
|Dual-Dirac+ Scope Histograms and BERTScan Measurements|
Introduction to Dual-Dirac.
|Evaluating Stress Components using BER-Based Jitter Measurements|
Self-verified jitter measurements using a BER-based Jitter Peak measurement.
|PCI Express® Transmitter PLL Testing — A Comparison of Methods|
Overview of significant methods for performing PLL Testing
|Stressed Eye: “Know What You’re Really Testing With”|
Using BER-based analysis to improve stress calibration measurements.
|Six Sigma’ Mask Testing with a BERTScope® Bit Error Rate Tester|
Using Six Sigma for citical insight.
|2017 Tektronix and Keithley Product Catalog|
Browse the new Tektronix and Keithley Product Catalog and explore our complete line of test and measurement solutions. You will find over 130 pages of key product details and specifications, application information, quick-reference selection guides and more for our complete line of products.