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Electrical Validation and Debug
DDR Memory Interface
Electrical validation solutions allow you to capture, measure and characterize DDR memory interfaced signal behavior, jitter, eye size, crossover, strobes/clock alignment and bit errors confidently with the MSO/DPO70000 Series of oscilloscopes that provide high waveform capture rates combined with sophisticated tools like Pinpoint Triggering, Visual Triggering and Advanced Search and Mark capabilities.
Probing solutions for P7700 and P7500 Tri-mode differential high-bandwidth probes combined with a wide variety of interposers provide access to those hard to reach signals.
Our memory signal analysis package supports all popular memory standards such as DDR1/2/3/4, LPDDR1/2/3/4, GDDR3/5 and automatically identifies and performs gated measurements on the acquired data to provide a comprehensive report that includes pass/fail results.
Automated measurements for compliance testing and debugging DDR3 and LPDDR3 are available as options on the 6 Series MSO.
Technologies | |||||||||
---|---|---|---|---|---|---|---|---|---|
Memory Technology | DDR | DDR2 | DDR2 | DDR3 | DDR3 | DDR3L | LPDDR3 | LPDDR4 | DDR4 |
Speed | all rates | Up to 400MT/s | Up to 800MT/s | Up to 1600MT/s | Up to 2400MT/s | Up to 1600MT/s | Up to 1600MT/s | Up to 4266MT/s | Up to 3200MT/s |
Max slew rate | 5 | 5 | 5 | 10 | 12 | 12 | 8 | 18 | 18 |
Typical V swing | 1.8 | 1.25 | 1.25 | 1 | 1 | 0.9 | 0.6 | 0.3 | 0.8 |
20-80 risetime (ps) | 216 | 150 | 150 | 60 | 50 | 45 | 45 | 27 | 27 |
Equivalent Edge BW | 1.9 | 2.7 | 2.7 | 6.7 | 8 | 8.9 | 8.9 | 15 | 15 |
Recommended Scope BW (Max Performance)* |
2.5 | 3.5 | 4 | 12.5 | 12.5 | 12.5 | 12.5 | 16 | 16 |
Recommended Scope BW (Typ Performance)* |
2.5 | 2.5 | 3.5 | 8 | 12.5 | 12.5 | 12.5 | 12.5 | 12.5 |
Oscilloscope Model | MSO/DPO 70404C |
MSO/DPO 70404C |
MSO/DPO 70404C |
MSO/DPO 70804C |
MSO/DPO 71254C |
MSO/DPO 71254C |
MSO/DPO 71254C |
MSO/DPO 7160C |
MSO/DPO 7160C |
Featured Content
DDR Electrical Verification and Memory System Debugging Webinar
This webinar will explain how to prepare for performing electrical verification testing for DDR-based memory designs in accordance to the latest JEDEC specifications. Learn how to get signal access to memory chips, and execute electrical verification tests with a comprehensive toolset from Tektronix.
Memory Interface Verification and Debug Webinar
Learn about the changes these new standards bring to electrical verification and how to prepare for proper signal access to LPDDR3 and DDR4 memory systems.
Electrical Verification of DDR Memory Application Note
This application note focuses on techniques for triggering and decode of the command bus and isolating read/write signals, as well as on a variety of memory signal integrity measurements.
Recommended Equipment
MSO/DPO70000 | The MSO/DPO70000 Series oscilloscopes deliver exceptional signal acquisition performance and analysis capability suitable for electrical verification and debug of the DDR memory interface. The digital channels on the MSO70000 models provide the ability to acquire and trigger on the events on the Address/Command bus. |
P7700 Probes | The P7700 high-bandwidth Tri-mode probes provide the ability to make accurate differential, single ended and common mode measurements. Unique DSP filters created for each probe and tip and an active buffer amplifier at the tip edge enable excellent signal fidelity for measuring high speed signals. |
P7500 Probes | The P7500 high-bandwidth Tri-mode probes provide the ability to make accurate differential, single ended and common mode measurements with one probe setup. |
Interposers | A comprehensive set of interposer solutions for all major JEDEC Memory standards. |
Opt. DDRA, Opt. LP-DDR4 | Complete memory interface analysis package for DDR1/2/3/4, LPDDR1/2/3/4 and GDDR3/5. Option LP-DDR4 for LPDDR4 is available to use only on MSO/DPO70000 Series oscilloscopes. |
Opt VET | Capturing and finding the right characteristic of a complex event on the DDR memory interface can require hours of collecting and sorting through thousands of acquisitions for the event of interest. The optional Visual Trigger makes the identification of the desired waveform events quick and easy. |
Opt DJA | DPOJET is a comprehensive jitter and eye-diagram analysis tool, that simplifies discovering signal integrity and jitter related issues in high-speed serial, digital, and communication system designs. |
Opt SDLA64 | The SDLA Visualizer enables complete measurement circuit de-embed, simulation circuit embed and receiver equalization. The SDLA Visualizer with DPOJET jitter and eye analysis provide a comprehensive simulation and measurement environment for computer, communications and memory buses. |
Opt 6-DBDDR3 | The 6 Series MSO, equipped with DDR3 Analysis and Advanced Jitter Analysis provides amplitude and time measurements specifically on DDR3 or LPDDR3 read, write, and read/write transfers. |
Opt 6-CMDDR3 | Automates DDR3 compliance testing on the 6 Series MSO. Combines with DDR3 Debugging and Advanced Jitter Analysis options for comprehensive debugging. |