Motorola MPC8260 ITR (PowerQuicc II) Microprocessor Support
- Full speed state analysis up to 66 MHz external bus frequency
- Cache enabled trace through Instruction Trace Reconstruction (ITR) which can decode the instructions when the cache is on.
- Supports the 60X compatible bus mode (SDRAM, GPCM) and Single 8260 mode (SDRAM, GPCM).
- Disassembly decodes and displays the processor's instruction set mnemonics.
- Symbolically identifies all processor bus cycles
- Acquired data can be linked directly to HLL source files for source level debug
- Up to 125 ps timing resolution enables detailed analysis of setup and hold times, edge-to-edge relationships, control timing, etc.
- All data acquired by the logic analyzer is time stamped to enable accurate time correlation of code execution to other system busses or hardware activity.
Engineers can design a probe interface directly into the system under test. This allows the greatest control of probe loading and provides the most mechanically robust connection. Tektronix recommends designing the P6860 connectorless or P6434 probe connectors into prototype models. Third party breakout boards are also available, providing an alternative probing method.
Minimum System Requirements
- TLA7xx mainframe and one TLA700 acquisition module, 136 channels, 100 MHz state (200 MHz state and up to 64M deep available)
- Or TLA600 instrument, 136 channels, 100 MHz state (200 MHz state and up to 1M deep available)
- P6860 Connectorless "compression" probes or,
- Qty 4: P6434 high-density mictor probes
- TLA application software V3.2 or greater
- Instrument setup software including clocking and channel assignments
- Symbol table of all bus cycle names
- Disassembler for MPC8260 processor
- User manual
Notes and Exceptions
Probe adapter is available from Ironwood Electronics
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