68030 Microprocessor Support

• Full speed state analysis up to 50 MHz for the 68030
  
• Full speed state analysis up to 40 MHz for the 68EC030
  
• Disassembly shows acquired data in the processor's instruction set mnemonics.
  
• Symbolically identifies all processor bus cycles
  
• Acquired data can be linked directly to HLL source files for source level debug
  
• 500 ps timing resolution enables detailed analysis of setup and hold times, edge-to-edge relationships, control timing, etc.
  
• All data acquired by the logic analyzer is time stamped to enable accurate time correlation of code execution to other system busses or hardware activity.
  

Probing and Package Styles

• 68030 probe adapter designed for a socketed 128-pin PGA package.
• 68EC030 probe adapter designed for a socketed 132-pin QFP package.
  

Minimum System Requirements

• TLA7xx mainframe and one TLA7L3 acquisition module, 102 channels, 100 MHz state, 32K deep (200 MHz state, 136 channels and up to 64M deep available)
  
• Or TLA603 instrument, 102 channels, 100 MHz state, 32K deep (200 MHz state, 136 channels and up to 1M deep available)
  
• qty 3: P6817 probes (included with acquisition module)
  
• TLA application software version 1.0 or greater
  

Package Includes

• Instrument setup software including clocking and channel assignments
• Symbol table of all bus cycle names
  
• Disassembler for 68030 and 68EC030 processors
  
• Probe adapter for ether a socketed 128-pin PGA package or 132-pin QFP package.
  
• User manual

Ordering Information

For information on availability and pricing, contact your Account Manager. 
For technical questions, please contact the Tektronix Support Center.