BERTScope® Clock Recovery
The BERTScope Clock Recovery CR Series advanced architecture measures and displays the PLL frequency response from 100 kHz to 12 MHz; the highest loop bandwidth available for jitter testing on the market today. The first clock recovery instruments to allow full control of parameters including loop bandwidth, peaking/damping, and roll off.
- Features and Benefits
- Software plus Downloadable
- Technical Documents
- Selection Guides
|Data Rate Range up to 28.6 Gb/s||Continuous data rate coverage for next generation I/Os including PCIe 3.0, 10GBASE-KR, 16xFC, 25 & 28G CEI and 100GBASE-LR-4 & ER-4.|
|Independent control, measurement, and display of phase lock loop (PLL) BW, JTF (jitter transfer function) and peaking.||Provides accurate "Golden PLL" response for transmitter jitter compliance testing and stressed receiver sensitivity test calibration. Provides full flexibility for device characterization.|
|Clock Recovery Input Equalization||Enables clock recovery on high ISI signals without impacting the data stream under test. Recovered clock enables other analysis including "clean eye", application of FIR filtering to signal, and BER testing.|
|Edge Density Measurement||Allows instant determination of the mark density of the signal under test.|
|Jitter Spectral Analysis and Frequency Gated Integrated Jitter Measurements||Provides 200 Hz to 90 MHz display of jitter vs frequency with cursor based measurements of jitter peaks' amplitude and frequency. Frequency gated integrated jitter measurements PCIe 2.0 compliance testing.|
|Optional 24 MHz PLL BW||Meets the JTF bandwidth requirements of USB 3.0, 6 G SATA, and PCIe-Gen 3.|
|Extensive set of subrate (recovered) clock outputs.||Frequently needed for device reference clocks.|
|100PSRTFILTER||100 ps Rise Time Filter|
|CR125ACBL||HIGH PERFORMANCE DELAY MATCHED CABLE SET (REQUIRED FOR BERTSCOPE & CRU IN SSC APPLICATIONS)|
|PMCABLE1M||Precision Phase Matched Cable Pair, 1m|
|Anatomy of an Eye Diagram|
Description of an eye diagram, how it is constructed, and common method for generating one.
|Clock Recovery’s Impact on Test and Measurement|
This application note discusses the outside influences that can disturb the relationship between data and how it is clocked.
|BERTScope® Bit Error Rate Testers Jitter Map “Under the Hood”|
A New Methodology for Jitter Separation
|Bridging the Gap Between BER and Eye Diagrams — A BER Contour Tutorial|
Introduction to the BER Contour measurement.
|Clock Recovery Primer, Part 1|
Look at clock recovery from a practical point of view, Part 1.
|Clock Recovery Primer, Part 2|
Look at clock recovery from a practical point of view, Part 2.
|Comparing Jitter Using a BERTScope® Bit Error Rate Testing|
Comparison of DCD and F/2 Jitter.
|Dual-Dirac+ Scope Histograms and BERTScan Measurements|
Introduction to Dual-Dirac.
|Evaluating Stress Components using BER-Based Jitter Measurements|
Self-verified jitter measurements using a BER-based Jitter Peak measurement.
|PCI Express® Transmitter PLL Testing — A Comparison of Methods|
Overview of significant methods for performing PLL Testing
|2017 Tektronix and Keithley Product Catalog|
Browse the new Tektronix and Keithley Product Catalog and explore our complete line of test and measurement solutions. You will find over 130 pages of key product details and specifications, application information, quick-reference selection guides and more for our complete line of products.