高速串列通訊

新一代的數位介面標準 (系列、記憶、顯示等) 迫使今日的相容性和偵錯工具本身限制面對多種高速 Tx 和 Rx 設計的問題，包括 -

裝置外型縮小而造成存取訊號受限
具備全新省電特性的匯流排行為
使用訊號介面來驗證新訊號編碼和等化的功能
備有多種電子驗證測試方法，為您省下更多時間！

Tektronix 提供可縮短 PHY 驗證週期，並確保一致性的自動化量測套件。若相容性量測失敗，也能利用通訊通訊協定解碼，和視覺觸發等工具加快除錯速度。從像是串流音或其他多線道雜訊耦合等，來源識別抖動與雜訊。

標準和技術

精選內容

PCIe、SAS、SATA 測試和除錯

若您想要跟上新一代資料速率和儲存標準的腳步，就需要有全面的解決方案，既可擴充到 32Gb/s，又可提供目前這代的功能。

探索如何加快設計測試和除錯。

深入瞭解

Type-C 的消費性電子產品標準

Type-C 接頭合併了 USB 3.1、DisplayPort 1.4，以及 Thunderbolt 等消費性電子產品標準，這會轉換為新的設計挑戰，難以既讓設計成本不高，又讓產品維持最佳的電子邊限。

探索如何應對這些新挑戰。

深入瞭解

高速介面標準的電子指南

這本免費的電子指南將協助您更進一步瞭解在測試 PCIe 4.0、SAS、SuperSpeed USB 和 DDR4 標準時，可能發生的設計問題。您可以快速取得相關的技術資源來瞭解設計問題，並選擇正確的解決方案來滿足您個人的測試需求。

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Library

Title
MIPI Debug and Conformance Testing Challenges and Solutions
以 16G 光纖通道速率分析 SFP + 收發器的特性研究針對 16G 光纖通道標準測試 SFP+ 收發器所需要的量測，涵蓋多模式 850 nm 和單一模式 Mode 1310 nm 介面。包含一個使用最新測試設備以 14.025 Gb/s 的 16G 線速率，單一模式 1310 nm 雷射 SFP+ 收發器進行。
PCI Express® 發射器 PLL 測試 - 方法比較有數種以所使用測試儀器類型為基礎量測 PLL 迴路回應的方法。如預期，多種方法會犧牲掉測試準確度、測試速度 (傳輸量)、易使用性、易設定性，和初始成本。此外，某些方法的限制使它們無法適用在所有類型的 PLL。所有的方法可以針對特定規格進行相容性測試，部分還提供額外有用的資訊供時脈設計工程師進行最佳化的設計。
PCIe Gen 5 Tx Tech Brief Background With the expected dramatic rise in the number of internetconnected devices and associated high bandwidth requirements of 5G and Internet of Things (IoT), data center …
High Speed Interface Standards This e-Guide will help you learn more about design challenges for testing PCIe 4.0, SAS, SuperSpeed USB, and DDR4 standards. Within the pages of the eGuide you will also get quick access to technical …
PCI Express Gen5 Automated Multi-Lane Testing Introduction Comprehensive characterization of high-speed links such as PCI Express® require performing measurements of the Transmitter (Tx) and Receiver (Rx) across multiple …
快速有效的 DVI 相容性量測挑戰解決方案 Tektronix 提供了所有您需要的 DVI 量測解決方案，從探測用的高頻寬數位螢光示波器 (DPO)，到特定應用軟體。Tektronix 解決了如抖動和眼狀圖測試等棘手的量測問題，打要可自動化和簡化您工作的 DVI 解決方案。
Probing Tips for High Performance Design and Measurement FIGURE 1. Probe loading is dependent upon the input impedance of the probe and the sensitivity of the circuit to this impedance. When …
Remote Head Acquisition Improves High Speed Serial Measurement As high speed serial data rates continue to increase, the need to maximize margin in measurements increases. Coaxial cables, even good quality ones can impact the measurement margin. Remote heads for …

Title
PCIe Gen5 to Gen6 and Comparison to Electrical Ethernet Watch as David Bouse explains the evolution of PCI Express from Gen5 to Gen6. Then hear from Pavel Zivny as he and David discuss PAM4 signaling in PCIe and how it compares with PAM4 as applied in …
How to Address Your Toughest Serial Bus Design Challenges with EDA and Measurement Correlation This Tektronix webinar will teach engineers how to use modeling tools to correlate simulations with high-speed physical layer measurements on Serial Bus Standards using the DPO/MSO70000 Series …
DDR5 Test Challenges Webinar Learn how you can address five of the thorniest measurement challenges associated with the new DDR5 standard. Get an update on the DDR5 Rx/Tx compliance test and insight in the latest characterization …
PCI Express Gen 4 and Gen 5 Transmitter and Receiver Validation PCI Express I/O bandwidth has doubled every 3 years on average thereby leading to an increased demand for this full duplex high speed bus architecture. As the industry begins deploying the 5.0 …
MIPI C-PHY D-PHY Webinar MIPI alliance standards have been driving the adoption of newer features and higher data rates for emerging mobile applications. Oscilloscope-based protocol layer validation enables isolating …
Demystify MIPI D-PHY and C-PHY Transmitter and Receiver Physical Layer Test During this webinar, you'll gain an understanding of MIPI test challenges for both MIPI high-speed physical layers. You'll also get useful tips and technical insights into characterizing and …
USB4 Webinar View our USB4 Compliance and Characterization Test webinar to learn how you can address the measurement challenges associated with the new USB4 standard.
PCIe Gen6 PAM4 Signaling Prepare for the next PCI Express inflection point by viewing this discussion of validation requirements for PCI Express Gen6. We review newly introduced transmitter measurements including SNDR and …
PCI Express Gen 5 Reference Clock Webinar This webinar presents an overview of reference clock jitter requirements as they have evolved and offers techniques for making these low femtosecond measurements using a real time oscilloscope.
DDR5 Memory Characterization While they promise to provide datacenters with large amounts of data at faster speeds and lower power consumption, DDR5 memory devices have unique test challenges. Learn about characterization and …
PCI Express Gen 5 Update Webinar Cloud-based computing power, storage capacity, and network bandwidth have led to the development of the PCI Express 5.0 specification for 32.0 GT/s. This webinar starts with an overview of 5.0 …