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High Speed Serial Communications Series

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Advanced Jitter and Noise Analysis

As serial data speeds increase, the need to perform accurate timing and jitter measurements is key to staying current in your design role. Check out this new webinar that covers advances in the popular DPOJET timing & jitter analysis toolset; including insights provided by amplitude based measurements.

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Measurement of Jitter Noise for Lower BER on High Speed PHY's


Designing and developing 100G (or 28G or 56G) components, modules and systems requires the latest tools and techniques. Our webinar covers: the differences between PAM and NRZ; the challenges with PAM signaling; recommended methodologies for validating PAM signals; and, transmitter and receiver test tools and techniques

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Fundamentals of Jitter Analysis


View this recorded webinar to get a solid overview of jitter components as well as jitter characterization and visualization. Learn how to control Jitter during system design and improve timing margins for today’s high-speed systems.

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Anatomy of Jitter


This webinar describes the different categories and types of jitter; the origins and interrelationships and how they can be used to diagnois, characterize and debug system hardware. Plus, explain how these various jitter measurements are applicable to your specific application.

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Avoiding Pitfalls in Jitter Measurements

Pitfalls in Jitter Measurements

This webinar discusses common pitfalls when making jitter measurements and how you can avoid them when making your measurements.

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High Resolution Display Interface Test on Mobile Platforms

This webinar takes a look at new display serial interface standards that support high resolution with lower power draw like DisplayPort over USB Type-C
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New Characterization Techniques for DDR4/LPDDR4 and Next Generation Memory Standards


This webinar provides an update on the latest characterization and debug techniques to enable analysis of the highest DDR4/LPDDR4 speed grades (DDR4-3200/LPDDR4-4266). Learn about:
  • New probing techniques to access the signals on the DRAM interface. 
  • Tools to enable you to quickly Capture, Identify, Analyze and Characterize the memory interface. 
  • New capabilities such as a decision feedback equalizer (DFE) and why they are being considered. 
  • What to expect from a debug and validation perspective for next generation Memory.

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Mobile Memory Testing: Preparing for Next Generation Standards

This webinar will explain how to prepare for next generation Mobile Memory testing. Learn about the changes new standards will bring to electrical verification and how to prepare for proper signal access to LPDDR3 and LPDDR4 mobile memory systems. Get advanced knowledge to plan for proper instrument selection needed for performing electrical verification tests on these emerging standards.

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Performing Hybrid Memory Cube Validation


New Hybrid Memory Cube technologies are providing tremendous potential for greater memory throughput on enterprise and desktop computing. Learn about the HMC technology and how to develop testing plans using Tektronix test equipment for HMC2.0 and HMC3.0.
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Efficiently Design and Electrically Validate a DDR4 Interface


This webinar will show how Cadence and Tektronix enable you with flexible and power efficient DDR4 IP, design and analysis tools used in the office, and lab-based solutions to address the key challenges in electrical validation of the DDR4 interface. Watch Now

Enterprise Networking Beyond 1Gbps: NBASE-T and IEEE802.3bz Technology and Measurements


The rapid growth of ever-more powerful mobile devices, and the adoption of new wireless technologies such as 802.11ac, has enterprise networks struggling to keep pace. To meet these rising bandwidth needs, network-access speeds must economically move beyond 1Gbps to 2.5G and 5G. The NBASE-T specification supports these faster speeds without requiring new cable runs which is key to keeping upgrade costs down. An overview of NBASE-T and the emerging IEEE802.3bz standard, as well as key measurement challenges, will be presented in this webinar.
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Demystify MIPI D-PHY and C-PHY Transmitter and Receiver Physical Layer Test


During this webinar, you'll gain an understanding of MIPI test challenges for both MIPI high-speed physical layers. You'll also get useful tips and technical insights into characterizing and validating design compliance as well as learning more about Tektronix’ own MIPI test solution. Live Q&A from the event is included at the end of the recording.
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