Customer Solution Summary
Challenge: The debug of ASIC prototypes is a major productivity bottleneck for Dini Group and its customers. Due to long FPGA re-compile times, debug is a slow and painful process when using traditional tools.
Solution: Version 2.0 of the Tektronix Certus ASIC Prototyping Debug Solution has given Dini Group designers direct access to thousands of RTL-level signals in their FPGAs, reducing the need to re-compile for each new set of debug probes and changing the way they approach overall FPGA debug.
Benefits: The Dini Group has realized significant time savings using Certus 2.0 primarily by reducing debug re-compile iterations. For one of their designs in the high-performance computing segment, each place and route iteration of the FPGA took more than three hours to complete. By using Certus 2.0 and speculatively instrumenting a large number of signals, Dini Group was able to reduce debug iterations from about 30 down to three, saving weeks of debug time on this one design alone.