In 1997, Tektronix introduced the award-winning TLA 700 Series logic analyzer family of products for digital design analysis. This card-modular instrument with MagniVu™ acquisition technology delivered, for the first time ever, 500 ps timing resolution simultaneous with up to 200 MS/s state acquisition on all channels. Now, Tektronix leverages the same technology in the newest and most affordable member of the TLA logic analyzer family, the TLA 600 Series.
As advanced semiconductor technology such as low-voltage CMOS proliferates into mainstream design, timing margins are getting tighter, propagation delays are shrinking and setup and hold times are moving well below 10 nanoseconds. This is true whether a designer is working with parts that clock at 16 MHz or 200 MHz (see Figure 1).
Most general-purpose logic analyzers just can't keep up as digital logic becomes faster throughout the electronics industry. Current conventional logic analyzers typically used by the vast majority of mainstream digital designers today only deliver, at best, 4 ns timing resolution on all channels; definitely less than what is needed to find subtle timing problems. Although logic analyzer manufacturers have gone to great lengths to make their analyzers as useful as possible-including halving channels to double acquisition rates which requires re-probing-it unfortunately is not good enough. Using less than adequate tools to solve difficult design problems is extraordinarily time-consuming and risky, but this is the normal practice in most development environments. To do their job effectively, designers require tools competent enough to stress and characterize the product to the point where they are sure the design and implementation are sound. The sooner designers can do this, the sooner the product can be released into the marketplace with confidence.
A Market-Driven Solution
Recognizing that the traditional paradigm for logic analyzers left much to be desired, Tektronix launched a major market research program to determine what designers really needed and wanted. What Tektronix found out was that digital designers needed more than eight times the timing resolution across all channels than what was available to measure setup and hold times in the 3-5 ns range.
These findings drove the development of Tektronix' breakthrough technology for digital design analysis. To create a new basis for logic analyzers, Tektronix leveraged its leadership position in oscilloscope technology, employing an asynchronous digital oversampling technology to provide in-depth analysis.
This oversampling technology was first incorporated in the card-modular TLA700 Series logic analyzer family and called MagniVu. It is this high-speed sampling architecture that enables these logic analyzers to deliver 500 ps timing resolution on all channels along with 200 MS/s synchronous state acquisition. In addition, new, high-speed probes with only 2.0 picofarad loading for the entire probe were designed to provide a single connection for both state and timing measurements, answering the desire for fewer and simpler connections to the system under test.
Introduced in 1997, the TLA 700 Series has been extremely well received by digital system designers. As a result, this modular series of logic analyzers has captured a majority of new sales for high-end logic analyzers. But as high-performance processors, ASICs, and buses become more common in mainstream design, especially embedded applications, design engineers that must operate within a limited budget are now clamoring for the same state-of-the-art analysis capabilities to help them create their next generation products. Anticipating this need, Tektronix focused on capturing the power of MagniVu acquisition technology in a family of affordable logic analyzers. This result is the TLA 600 Series.
Similar to the TLA 700 Series, this new family of lower-cost logic analyzers delivers simultaneous 500 ps timing and up to 200 MS/s synchronous state acquisition on each and every channel. This architecture ensures that the TLA 600 Series gathers a complete picture of the design's operation, providing simultaneous 2-GHz timing and up to 200-MHz state analysis. The MagniVu technology is coupled with up to 1 M/sample of state and main timing memory and 2k of high-speed timing memory. This high-speed timing memory can provide enough high-speed memory to store 1 µs worth of data for each channel, which is up to 50 bus cycles worth of information for today's leading processors. Best of all, only one set of probes needs to be attached to the circuit under test to acquire both state and timing information. It is also the first logic analyzer in its class to offer an Open Microsoft Windows® user interface and PC platform that easily integrates into the design environment.
The Power of Oversampling
The asynchronous digital oversampling architecture at the heart of MagniVu acquires all input signals including clocks, asynchronously with a full-custom, high-speed digital sampling front end. Sampling at the rate of 2 GS/s, this chip supports 500 ps timing resolution on all channels (see Figure 2).
|What is remarkable is that this 500 ps resolution is achieved using circuitry driven by a 250 MHz clock. Conventional design wisdom states that clock acquisition circuitry must be at least the same speed as its maximum sample rate. A gigahertz clock, for instance, is needed for 1 GS/s sample rate. However, by leveraging key elements of proven Tektronix oscilloscope technology, our engineers defied convention and came up with a better implementation. Instead of scaling conventional techniques to gigahertz clock rates, which would be extremely expensive and risky, they took a slower, 250-MHz clock and built a delay chain composed of eight 500-picosecond (ps) delays to clock a set of eight sampling circuits.|
For every 4 ns tick of the 250 MHz clock, eight samples are acquired at 500 ps intervals for each channel. Since all this information is processed digitally after sampling, there is no degradation of the signal and minimal skew.
Each consecutive eight bits of sampled data are loaded in parallel every 4 ns into a shift register that feeds out selected pieces of the data to a 1M memory based on user-defined, clocking, triggering and storage parameters. This large memory, implemented off-chip using common RAM devices, can store data asynchronously acquired at up to 250 MS/s or synchronously acquired state acquisition at up to 200 MS/s for all channels at all times.
At the same time, another high-speed memory 2k samples deep, implemented on-chip as a custom array, directly stores the unconditioned stream of data straight from the sampler for each channel. This high-speed memory is large enough to store one microsecond worth of data for each channel. So, as the overall state activity is stored in the larger, slower memory, complete timing information is simultaneously captured in this faster memory.
MagniVu's dual memory architecture ensures that the TLA 600 Series gathers a complete picture of the design's operation during state analysis, providing simultaneous 2-GHz timing and 200-MHz state analysis. Since both the state and timing information are derived from the same stream of oversampled data, only one set of probes needs to be attached to the circuit under test. Furthermore, since the state and timing are derived from the same 2 GHz sampler, there is absolute time correlation between the two. Only MagniVu's unique architecture can achieve this level of accuracy between state and timing.
The super-fast sampler enables the TLA 600 Series logic analyzers to offer 500 ps timing resolution on all channels. Now when an anomaly occurs, the designer can zoom in and examine exactly what occurred in 500 ps resolution without re-acquiring the data. This is true for each and every channel-up to 136 per instrument-and for each and every acquisition. As a result, the TLA 600 Series literally enables designers to see all the details on all channels when troubleshooting. Finding subtle timing problems-glitches, delays or noise-is a much faster and easier with this resolution on all channels.
The TLA 600 Series and its remarkable resolution greatly streamlines the troubleshooting process. With MagniVu, the TLA 600 Series can acquire asynchronous and synchronous data simultaneously for each and every acquisition. So even if a state acquisition is specified, the designer can still view the asynchronous acquisition at any time, without having to re-acquire. That means when a problem occurs, the designer can immediately zoom in and examine the detailed behavior of all the signals with 500 ps resolution.
Finding subtle timing problems-glitches, delays or noise-is now a straightforward process with 500 ps resolution on all channels. Designers can hunt for the root causes of problems in detail across all the channels right when they occur. This is especially useful for troublesome anomalies that occur infrequently. For example, the processor reads a value that is invalid and causes the application to fail. After triggering the logic analyzer on the faulty read cycle, the designer can use MagniVu to see the detailed timing of every signal around the critical event that triggered the current acquisition (see Figure 3).
|Until now, finding glitches has been a cumbersome process. However, thanks to asynchronous digital oversampling, the TLA 600 Series can automatically hunt for glitches on every channel with sub-nanosecond resolution. The glitch detector monitors the high-speed data stream out of the sampler. When a glitch occurs, the detector triggers the analyzer. The designer then can use MagniVu to actually see the number, width, and placement of glitches within the sample period with 500 ps resolution.|
|Moreover, the TLA 600 Series can directly trigger on violations of the most crucial synchronous timing parameters-setup and hold time. The setup and hold checker detects transitions in the input signals after they are acquired with the high-speed digital sampler. The transitions are then skew adjusted and violations are flagged if the transitions are within the interval defined by the user.|
Comprehensive Timing Verification
The benefits of asynchronous digital oversampling don't stop with improved troubleshooting and state analysis. With 500 ps resolution, the TLA 600 Series is equipped to perform full-fledged timing analysis.
MagniVu enables the TLA 600 Series to produce extremely precise time stamps-an important feature for characterizing clock stability. Time stamps values are derived by identifying the precise placement of the clock edge in the oversampled data stream of the specified clock signal. The result is exceptional 500 ps resolution stamping that is an eight to 16 times improvement over other logic analyzers.
The expanded capabilities of the TLA 600 Series dramatically streamline the entire hardware verification process for the designer. Instead of using several instruments and having to struggle with multiple sets of probes, they simply attach one set. Now designers can directly verify the design against detailed timing simulations, viewing the timing of clocks, data and address signals with respect to each other and asynchronous inputs.
For example, with the TLA 600 Series connected, designers can easily characterize clock signals for the entire clock distribution. They can also exhaustively examine the performance of a system's data bus with this logic analyzer. Even the margins for setup and hold can be characterized, to the give the designer an idea of how well the circuitry will accommodate component and temperature variations. Special capabilities are included to help the designer scrutinize the interaction between address, data and control lines. In fact, the entire bus cycle can be stored as a single synchronous transaction with a timestamp indicating the precise time at which the cycle was completed. Finally, the designer can use the TLA 600 Series to trigger on combinations of hardware and software events and view the timing that caused them.
A New Breed of Logic Analyzer
With the TLA 600 Series, Tektronix has successfully created a new paradigm for logic analyzers that meets the demands of today's and tomorrow's processor-based designs. The innovative asynchronous digital oversampling technology at the heart of the TLA 600 Series supports faster acquisition across dozens of channels with deep memories to keep pace with rapidly advancing digital design technology. With its 500-ps timing resolution, digital designers will be able to see details of system timing they could never see before by using traditional logic analyzers. Moreover, this technology provides new measurement capabilities that dramatically expand the role of the logic analyzer in design debug and verification. No other monolithic logic analyzer delivers all this in one, affordable package.