The PCI-SIG® has continued to execute on the aggressive goal to double data rates with each successive generation of the PCIe® standard since the first generation was released in 2003. While these radical data rate increases have positively affected the high-speed I/O (HSIO) device industry – primarily in PC components, data centers, and most recently, automobiles – the time it takes to evaluate new PCIe device designs is becoming more of a bottleneck for development. Test tools such as bit error rate testers (BERTs) and oscilloscopes continue to evolve to meet the performance requirements of each new generation, but reductions in testing times have not been at the forefront of improvements in these performance tools.
Figure 1 Increases in Data Transfer Rates with Each Generation of PCI Express.
What are some of the factors that contribute to this increasing test time? Of course, there’s the inherent complexity caused by the increasing data rates themselves, which introduce more signal integrity issues and longer debug processes than previous generations. The consequences associated with failing to address these signal integrity issues, or thoroughly debug designs before launch, are always costly in terms of product recalls or missing key market windows. The need to bring products to market sooner, with little room for error, places a heavier burden on validation teams with each new generation of the PCIe standard. This burden is only amplified by the fact that teams are still armed with the same legacy test equipment that is focused more on performance improvements than test time reduction.
But what if there were an additional tool, one that could be used more frequently throughout development to identify issues early and often? That’s the concept behind the Tektronix TMT4 Margin Tester. It’s not a replacement for BERT/Scope systems, nor does it replace the on-chip lane margining (LM) tools available from silicon manufacturers. Instead, the TMT4 Margin Tester is a dedicated transmit/receive lane margining tool that allows users to capture link health issues with PCIe Gen 3 and Gen 4 devices in minutes. This reduction in test time complements the performance of Scope/BERT systems, and the TMT4’s Tx testing capabilities nicely complement the Rx testing capabilities of LM tools from silicon vendors.
Easy to set up and operate, TMT4 generates eye diagrams. This quick snapshot enables faster resolution of gross link performance issues by showing design and validation teams where their problems might be, if any, in just minutes.
Figure 2. Eye Diagrams Are Presented to the User by the TMT4 Margin Tester in Real Time.
In addition to displaying eye diagrams, the Margin Tester also provides insight into the equalization its receivers used to maximize the height and width of the generated eye. This can often be critical information as some eyes may need especially high levels of equalization to form the link, and that is often not immediately apparent when looking at the eye diagrams in isolation.
Figure 3. Link Training Parameters of the Margin Tester Receivers Provide Additional Insights into Potential Link Health Issues
Given that setup can be completed in less than ten minutes, and results available in as little as 2 minutes, frequent performance checks of the link are made possible with the tool’s Quick Scan feature. It enables a fast view of link health after undergoing natural link training and negotiations between a DUT and the TMT4 Margin Tester. And when a user needs to initiate a deeper investigation into specific lane-preset combinations or needs to perform a more comprehensive test of all lanes and presets, the Custom Scan feature offers these capabilities.
Figure 4. Quick Scan Results Table with Link Training Parameters (top left), Eye Diagrams (top right), and Rx Test (bottom).
The TMT4 Margin Tester supports most of the common PCIe form factors like CEM, M.2, U.2, and U.3, enabling it to link with the majority of the PCIe devices available today. Focused on fast test times, ease of use, and providing a cost-effective testing solution to the PCIe market, the TMT4 Margin Tester provides the industry with a much-needed complementary tool for any PCIe design or validation lab. Faster testing enables more frequent testing without the negative schedule impacts, and more frequent testing enables teams to identify problems earlier in the development cycle. This is one way by which Tektronix believes the TMT4 will accelerate product development and nicely complement existing PCIe testing solutions. Learn more about TMT4 Margin Tester as well as our full line of PCI Express solutions online.
Figure 5. TMT4 Margin Tester (center), CEM Edge Adapter (right) and Networked Access to Results on PC (left).