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Tektronix PCI Express

PCI Express Receiver Test Suite Datasheet

線上參閱:

Improve accuracy and precision of PCI Express Gen5 Receiver Stressed Eye Calibration, Receiver & Transmitter Link Equalization testing, and Receiver Jitter Tolerance with Tektronix automation software. Remove the complexity of receiver testing with a step-by-step user interface designed by industry leaders engaged in the standards bodies to drive the latest specifications to maturity. Industry engagement ensures our software will evolve in-step with the technology. Achieving the correct balance of simplicity and user control has been at the forefront of the design team to ensure your device can complete link training with the correct calibrated stress and be efficiently tested with optimized PHY settings.

Applications

  • PCI Express Gen5 (32 GT/s) & Gen4 (16 GT/s)
  • Gen5 Base Specification (silicon validation) & Gen5 and Gen5 CEM Specification (system verification & compliance)
  • Root Complex & Non-Root Complex silicon
  • Systems (motherboards & servers), Add-in Cards, Switches & Bridges, Extension Devices (retimers & redrivers)

Features and benefits

PCI Express Gen5 (32 GT/s)

  • Receiver automation software for Tektronix DPO70000SX Series Real Time Scopes & Anritsu MP1900A BERT
  • Wizard based user interface for each step of calibration and test
  • Pop-up user tips to simplify decision making
  • Stressed Eye Calibration (32 GT/s) &
    • Base & CEM
    • TP3 – AC/DC Balance, Amplitude, Tx Equalization, Sinusoidal Jitter tones, & Random Jitter
    • TP2 – DMI, CMI, Preset & CTLE Selection, Stressed Eye, Automated loopback through Configuration & Recovery
  • Insertions Loss computation powered by Seasim Statistical Simulation Tool
  • Rx Link Equalization (32 GT/s)
  • Tx Link Equalization (32 GT/s)
  • Jitter Tolerance (32 GT/s)
  • Latest industry tool support (SigTest & Seasim)
  • Calibration and test reports

PCI Express Gen4 (16 GT/s)

  • Receiver automation software for Tektronix DPO70000SX Series Real Time Scopes & Anritsu MP1900A BERT
  • Wizard based user interface for each step of calibration and test
  • Pop-up user tips to simplify decision making
  • Stressed Eye Calibration (32 GT/s)
    • CEM
    • TP1 – AC/DC Balance, Amplitude, Tx Equalization, Sinusoidal Jitter tones, & Random Jitter
  • TP2 – DMI, CMI, Preset & CTLE Selection, Stressed Eye, Automated loopback through Configuration & Recovery
  • Insertions Loss computation powered by Seasim Statistical Simulation Tool
  • Rx Link Equalization (16 GT/s)
  • Tx Link Equalization (16 GT/s)
  • Jitter Tolerance (16 GT/s)
  • Latest industry tool support (SigTest & Seasim)
  • Calibration and test reports

Stressed Eye Calibration

Calibration of the stressed eye signal, generated by the BERT’s PPG, is important to ensure the receiver is tested in alignment with the PCI-SIG specifications with the proper amount of impairments. New challenges at 32 GT/s demand the fully automated approach taken by the Tektronix PCI Express Receiver Test Suite to avoid alternative tedious and error-prone approaches. Let the domain expertise and experience of the Tektronix engineers guide you through the steps of calibration starting with accurate TP3 measurements and ending with an end of channel eye diagram easily obtained within the tolerances required. Engineers will spend less time calibrating and more time collecting meaningful data on receiver performance and margin.

TP3 calibration

PCI Express Gen5 (32 GT/s)

The TP3 (cable from BERT PPG to scope) is mandatory for all devices to ensure tolerances are met at the defined reference plane. Tek Tektronix PCI Express Receiver Test Suite wizard will guide the user through all the necessary steps to pre-channel signal is true to the specification requirements to ensure future calibration steps complete with ease.

  1. AC-DC Balance – Small amounts of Tx EQ de-emphasis are enabled to balance low and high-frequency sections of the pattern at a common reference plane.
  2. Amplitude – The differential voltage swing is required to be within 720 – 800 mV.
  3. Tx Equalization Presets – Calibration of pre-shoot and de-emphasis is required to ensure true preset level are used for testing receivers.
  4. IL Measurement – Channel insertion loss is calculated using Seasim between TP3 and TP1 (loss before the TP3 reference is computed here for later removal).
  5. RJ – Random Jitter (RJ) is calibrated to be 0.5 ps (RMS value) nominally.
  6. SJ – Sinusoidal Jitter (SJ) is calibrated over the required range of 1-5 ps (p-p) including the nominal SJ specification of 0.1 UI (or 3.125 ps) at 100 MHz frequency.
  7. [email protected] MHz – This calibration is required for JTOL measurements with some calibrations
    PCIe Rx Gen4_Gen5_EN US_61W 73782 1
  8. Multi-tone SJ – For JTOL measurements where up to maximum 14 frequencies are used, calibration for frequencies other than 100 MHz are required to be performed.
PCIe Rx Gen4_Gen5_EN US_61W 73782 1
RJ/SJ calibration

Automatic characterization and precise calibration of presets, RJ, and SJ along with the important parameters used for calibration like pattern type, scope, BERT settings, regression line slopes, and intercept for reference.

TP1 calibration

PCI Express Gen4 (16 GT/s)

The TP1 (cable from BERT PPG to scope) is mandatory for all devices to ensure tolerances are met at the defined reference plane. Tek Tektronix PCI Express Receiver Test Suite wizard will guide the user through all the necessary steps to pre-channel signal is true to the specification requirements to ensure future calibration steps complete with ease.

  1. AC-DC Balance – Small amounts of Tx EQ de-emphasis are enabled to balance low and high-frequency sections of the pattern at a common reference plane.
  2. Amplitude – The differential voltage swing is required to be within 720 – 800 mV.
  3. Tx Equalization Presets – Calibration of pre-shoot and de-emphasis is required to ensure true preset level are used for testing receivers.
  4. IL Measurement – Channel insertion loss is calculated using Seasim between TP3 and TP1 (loss before the TP3 reference is computed here for later removal).
    PCIe Rx Gen4_Gen5_EN US_61W 73782 1
  5. RJ – Random Jitter (RJ) is calibrated to be 1 ps (RMS value) nominally.
  6. SJ – Sinusoidal Jitter (SJ) is calibrated over the required range of 5-10 ps (p-p) including the nominal SJ specification of 0.1 UI (or 6.25 ps) at 100 MHz frequency.
  7. [email protected] MHz – This calibration is required for JTOL measurements with some calibrations.
    PCIe Rx Gen4_Gen5_EN US_61W 73782 1
  8. Multi-tone SJ – For JTOL measurements where up to maximum 14 frequencies are used, calibration for frequencies other than 100 MHz are required to be performed.

PCIe Rx Gen4_Gen5_EN US_61W 73782 1
Example Report:

Automatic characterization and precise calibration of presets, RJ, and SJ along with the important parameters used for calibration like pattern type, scope, BERT settings, regression line slopes, and intercept for reference.

TP2 calibration

PCI Express Gen5 (32 GT/s) & Gen4 (16GT/s)

The TP2 (end of the channel) calibration is a complex process requiring a deep understanding of the BERT, Real Time Oscilloscope, post-processing tools, and the PCIe specifications. The Tektronix PCI Express Receiver Test Suite will remove the complexity and ensure the desired results are achieved through user-friendly automation. Time to TP2 completion is critical, so efficient techniques have been Implemented to ensure an accurate stressed eye is achieved within a reasonable time scale. From calibration of DMI (differential mode interference modeling cross-talk) to the fine granularity adjustments to SJ and DMI necessary to find the stressed eye solutions space, our automation software will guide you through this otherwise daunting task.

  1. DMI– The differential mode interference is required to be calibrated within 5-30 mV (p-p) [Gen5] / 10-25 mV (p-p) [Gen4] by capturing the 2.1 GHz sinusoidal output for a duration of 40 ns.
  2. CMI – The common-mode interference is required to be calibrated for a nominal voltage of 150 mV (p-p) by capturing the 120 MHz sinusoidal output for a duration of 62.5 us.
  3. Channel insertion loss for DMI/CMI & eye diagram measurements computed with Seasim (TP1 to TP2/TP2P for 16GT/s & TP3 to TP2/TP2P for 32GT/s).
  4. Channel Selection based on optimal Tx EQ Preset and Rx CTLE – Base Specification compliant for Eye Area criteria and tie breaker rules.
  5. Stressed-Eye calibration – Fine-tuning of the eye using amplitude, SJ, & DMI is utilized to place the stressed eye within allowed tolerances.
    PCIe Rx Gen4_Gen5_EN US_61W 73782 1PCIe Rx Gen4_Gen5_EN US_61W 73782 1PCIe Rx Gen4_Gen5_EN US_61W 73782 1PCIe Rx Gen4_Gen5_EN US_61W 73782 1
    AIC TP2 calibration results
    PCIe Rx Gen4_Gen5_EN US_61W 73782 1
    Stressed eye calibration result

    Automated TP2 calibration plots and stressed eye calibration details along with other important parameters like pattern type, scope and BERT settings and regression line slopes and intercept for reference.

  6. Eye height 15 +/- 1.5 mV [Gen5 & Gen4] and
    • Eye width 9.375 +/- 0.5ps [Gen5]
    • Eye width 18.75 +/- 0.55ps [Gen4]

Link training

Prior to receiver testing, the device-under-test (DUT) must be placed into loopback, where the data digitized at the Rx latch is re-transmitted by the corresponding Tx giving visibility into a possible bit or burst errors. Entering the loopback test mode requires a complex dance through the Link Training Status State Machine (LTSSM) between the BERT and DUT. The Tektronix PCI Express Receiver Test Suite automates this sequence allowing loopback through configuration (short path) and loopback through recovery (full training of the link Tx & Rx) for different levels of receiver testing. Relevant parameters are exposed to allow user control over this process without unnecessary complexity.

PCIe Rx Gen4_Gen5_EN US_61W 73782 1PCIe Rx Gen4_Gen5_EN US_61W 73782 1
Flexible link training and loopback control

Receiver and transmitter link equalization testing

PCI Express compliance at 32 GT/s & 16 GT/s requires performing a Receiver Link Equalization test (checking analog Rx performance with a stressed signal after full link training) and a Transmitter Link Equalization test (ensuring key digital timing limits are achieved when an Rx makes Tx change requests to its link partner).

The Tektronix PCI Express Receiver Test Suite controls the BERT and RT Oscilloscope during these required tests to provide efficient test results with minimal overhead and control only where needed.

PCIe Rx Gen4_Gen5_EN US_61W 73782 1PCIe Rx Gen4_Gen5_EN US_61W 73782 1
Tx-LEQ and Rx-LEQ test configuration
PCIe Rx Gen4_Gen5_EN US_61W 73782 1PCIe Rx Gen4_Gen5_EN US_61W 73782 1
Tx-LEQ and Rx-LEQ execution page
PCIe Rx Gen4_Gen5_EN US_61W 73782 1
Tx-LEQ AIC Response time test results
PCIe Rx Gen4_Gen5_EN US_61W 73782 1
AIC Rx LEQ test results

Remote control protocol

The test software can be operated remotely through ASCII commands sent through TCP/IP, giving engineers further flexibility in designing “Beyond Compliance” tests.

Jitter Tolerance (JTOL) test

Jitter tolerance (JTOL) testing requires sweeping numerous calibrated SJ tones from low to high amplitude to see how the receiver-under-test CDR tracks the stress (typically in the presence of other noise & jitter sources). Custom JTOL pass/fail masks can be configured while testing with different search algorithms (upward linear, logarithmic, etc. …). The Tektronix PCI Express Receiver Test Suite allows engineers minimal setup with quick and descriptive test reports.

PCIe Rx Gen4_Gen5_EN US_61W 73782 1
JTOL test configuration settings

Both the custom mask and the specification mask are provided in the JTOL test to have a better understanding of the DUT performance, especially at the design stage. The Receiver solution performs an automatic back channel equalization and sampling point optimization ensures to ensure the best conditions for the DUT transmitted data traffic to be accurately comprehended at the BERT receiver to ensure the correct determination of BER performance.

PCIe Rx Gen4_Gen5_EN US_61W 73782 1
JTOL test result with specification
PCIe Rx Gen4_Gen5_EN US_61W 73782 1
Error detector and stress settings for JTOL
PCIe Rx Gen4_Gen5_EN US_61W 73782 1
Different margin search algorithm settings for JTOL test

Ordering information

PCIe Gen5 Base and CEM Software Options

Models - SX >= 50 GHz DPS + DPO
ItemDescriptionType
RXSW-NL1-PCIE5License; PCI Gen 5 Rx CEM and BASE automation software for TEK scopes and Anritsu BERT; Node-Locked 1-Year SubscriptionSoftware
RXSW-NLP-PCIE5License; PCI Gen 5 Rx CEM and BASE automation software for TEK scopes and Anritsu BERT; Node-Locked PerpetualSoftware
RXSW-FL1-PCIE5License; PCI Gen 5 Rx CEM and BASE automation software for TEK scopes and Anritsu BERT; Floating 1-Year SubscriptionSoftware
RXSW-FLP-PCIE5License; PCI Gen 5 Rx CEM and BASE automation software for TEK scopes and Anritsu BERT; Floating PerpetualSoftware

PCIe Gen5 Pre-compliance Fixture Options

ItemDescriptionType
TF-PCIE5-CEM-X16PCIe Gen5 X1/X4/X8/X16 Electrical Test Fixture, Supports X1/X4/X8/X16 configuration includes ISS Board, CBB (System Board), CLB X1-X16, CLB X4-X8, 4 MMPX cables, and 4 MMPX to 2.92 mm cablesFixture
TF-PCIE5-CEM-X1PCIe Gen5 X1/X16 Electrical Test Fixture, Supports X1/X16 configuration includes ISS Board, CBB (System Board), CLB X1-X16, 4 MMPX cables, and 4 MMPX to 2.92 mm cablesFixture

PCIe Gen4 CEM Software Options

Models >= 24 GHz and Above (DPO72504DX, DPO73304DX, DPO70KDX)
ItemDescriptionType
RXSW-NL1-PCIE4CLicense; PCI Gen 4 Rx CEM automation software for TEK scopes and Anritsu BERT; Node-Locked 1-Year SubscriptionSoftware
RXSW-NLP-PCIE4CLicense; PCI Gen 4 Rx CEM automation software for TEK scopes and Anritsu BERT; Node-Locked PerpetualSoftware
RXSW-FL1-PCIE4CLicense; PCI Gen 4 Rx CEM automation software for TEK scopes and Anritsu BERT; Floating 1-Year SubscriptionSoftware
RXSW-FLP-PCIE4CLicense; PCI Gen 5 Rx CEM automation software for TEK scopes and Anritsu BERT; Floating PerpetualSoftware

Overall Setup list:

PCIe Gen5 Base Rx
ItemVendorTypeR/OQtyDescriptionNotes
DPS75004SXTektronixEquipmentRequired1Dual-Stack 50 GHz Sx Scope 50 G or better1
DPO7RFK2Tektronix Tek accessoryRequired2Attenuator kitAttenuator kit + DC blocks
103047400Tektronix Tek accessoryRequired2Connector savers (1.85 mm)1.85 mm scope channel input connection
Anritsu MP1900A5Anritsu3rd party equipmentRequired1Bit Error Rate Tester (BERT)2Configuration provided by 3rd party
DJATektronixEquipment SW option Required1DPOJET advanced optionDPOJET advanced option
SDLA64TektronixEquipment SW option Required1Serial Data Link Analysis (SDLA) SoftwareSerial Data Link Analysis (SDLA) Software
174-6659-01TektronixTek accessoryRequired1 prCable; SMA - SMP cable pairRefclk connection between DUT & BERT
PMCABLE1MSwiftbridgeTek accessoryRequired2 prCable; 2.92-to-2.92 mm, Straight, 1.5 ps phase-matched, 40 GHzEquipment connections to relica channel & DUT
Gen5 Base Test Fixture SetPCI-SIGTest fixturesRequired1Gen 5 Base Rev3 Test Fixtures3Rev3 is Meg6 material with MMPX connectors4
RXSW-XXX-PCI5Tektronix SW optionRequired1 PCIe Gen5 Receiver Software Select from Node locked Perpetual /1 year subscription
PCIe Gen5 CEM LEQ
ItemVendorTypeR/OQtyDescriptionNotes
DPS75004SXTektronixEquipmentRequired1Dual Stack 50 GHz Sx scope 50 G or better1
DPO7RFK2Tektronix Tek accessoryRequired2Attenuator kitAttenuator kit + DC blocks
103047400Tektronix Tek accessoryRequired2Connector savers (1.85 mm)1.85 mm scope channel input connection
Anritsu MP1900A5Anritsu3rd party equipmentRequired1Bit Error Rate Tester (BERT) 2Configuration provided by 3rd party
DJATektronixEquipment SW option Required1DPOJET advanced optionDPOJET advanced option
SDLA64TektronixEquipment SW option Required1Serial Data Link Analysis (SDLA) softwareSerial Data Link Analysis (SDLA) software
PMCABLE1MTektronixTek accessoryRequired2 prCable; 2.92-to-2.92 mm, straight, 1.5 ps phase-matched, 40 GHzEquipment connection to fixtures and DUT
174-6663-01TektronixTek accessoryRequired1 prCable; 2.92-to-2.92 mm, straight, 1.5 ps phase-matched, 500 mm, 40 GHzSignal connection between scope and BERT for Tx LEQ
174-6666-01TektronixTek accessoryRequired2 prCable; SMA-to-SMA, Right Angle-Right Angle, 500 mmSignal connection between scope and BERT for Tx LEQ & Trigger
174-6659-01TektronixTek accessoryRequired1 prCable; SMA - SMP cable pairRefclk connection between DUT & BERT
MPR40MFairview Microwave3rd partyRequired2Power dividerSplit signal from DUT Tx to the scope and Error Detector
C7035CentricRF3rd partyOptional 4Right Angle Male-Female 2.92 mm adapterCable management
C7049CentricRF3rd partyRequired32.92 mm Male to 2.92 mm Male adaptor Power divider output to scope input
Redriver3rd party3rd party equipmentOptional1Active Gen5 Redriver (back channel equalization)6High loss back channels (DUT Tx to Error Detector) may need EQ
PowerUSB - BasicPowerUSB3rd partyOptional1Power USB Power StripAutomate DUT power cycle
TF-PCIE5-CEM-X16Tektronix or PCI-SIGTest fixturesRequired1Gen 5 CEM Test fixtures7Tektronix fixtures are not officially approved by PCI-SIG4
RXSW-XXX-PCI5Tektronix SW optionRequired1 PCIe Gen5 Receiver software Select from Node locked Perpetual /1 year subscription
PCIe Gen4 CEM
Equipment Details Qty Vender
Bit Error Rate Tester (BERT) Part Number provided by 3rd Party 1Anritsu
Real Time Oscilloscope > 24 GHz DPO72504DX, DPO73304DX, DPO70KDX 1Tektronix
DPOJET Advanced option DJA (Scope SW option) 1Tektronix
1-m Cable pair (2.92 mm SMA Male - SMP ) 174-6659-01 (DUT-BERT Ref clock) 1 pair Tektronix
1 m Cable (2.92 mm M-M, Straight, 1.5 ps phase - matched, 40 GHz) PMCABLE1M (Equipment connection to fixtures and DUT) 2 pairs Tektronix
0.5 m Cable (2.92 mm M-M, Straight, 1.5 ps phase - matched, 40 GHz) 174-6663-01 (Signal Connection between scope and BERT for Tx LEQ) 1 pair Tektronix
0.5 m Cable (SMA M-M, Right Angle - Right Angle) 174-6666-01 (Connection between scope and BERT for Tx LEQ & Trigger)2 pairs Tektronix
Power Divider (2 way 2.92mm F-F-M) MPR40M (Split signal from DUT Tx to the scope and Error Detector) 1 pair Fairview Microwave
Power USB Power Strip PowerUSB – Basic (Automate DUT power cycle) PowerUSB
SMP 50 Ohm Terminator 50 ohms (Female) **Any
ATX Power Supply for System Board Power Any 1Any
Gen 4 CEM Test Fixtures PCI-SIG 1PCI-SIG
EqualizerBSXPCI4EQ 2Tektronix
Optional Items
Right Angle M-F 2.92 mm adapter C7035 (Cable management) 4CentricRF
Active Gen4 Redriver (Back channel equalization) - 1Texas Instrument
Host system software requirements
Microsoft Windows 10

1If ATI channels will be used for refclk measurements they will need Option Key 4 (50 XL)

2Cables required for connection between BERT modules shall be included for the 3rd party vendor

3Gen5 BaseTest Fixtures are not backwards compatible for Gen3 & Gen4 Base Rx

4It is assumed MMPX cables and MMPX to SMA adaptor cables for test fixture connections are included with the fixture kit

5Configuration for BERT provided by 3rd party vendor

6Another matched pair of cables (e.g. 174-6663-xx) will be required if the Active redriver is used for Rx or Tx LEQ

7Gen5 CEM Test Fixtures are not backwards compatible for Gen3 & Gen4 CEM Rx