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How does the logic analyzer implement transitional timing?

질문:

How does the logic analyzer implement transitional timing?

답변:

All data is sampled using the logic analyzer's internal sample clock that can be varied from the minimum sample interval of 2ns to 50 msec.

Transitional Storage mode works when using either internal or external clocking. The Storage feature in the LA trigger menu controls the actual data stored into memory. If Transitional Storage is selected, a special transition detector is enabled that causes only two consecutive samples that differ to be stored. If two consecutive samples are identical, then no sample is stored. Of course, all acquired data is timestamped with a 51-bit 500 ps timestamp so that accurate data correlation can be made over a long period of time or ~6.5 days.

*Minimum sample interval is 4ns for TLA6xx Series, TLA704 and older modules.


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