As design margins shrink, accurate and standard-specific measurement is key to debugging, verifying design and performing interoperability testing when designing PCIe devices. Having confidence in test processes, workflows and results will allow you to reach compliance faster. This webinar will provide the information you need to do just that.
We will discuss the most recent PCIe 3.0 and 4.0 versions and provide an in-depth look at: PCIe Trends and Architecture PCIe Transmitter (Tx) and Receiver (Rx) Compliance Testing Current Testing Challenges and Solutions for both Tx and Rx Key Enhancements of Gen4 PCIe Debugging Loopback Initiation and Link Training with Tek’s new protocol-aware BERTScope
기간 53m 34s
