The recent advent of Rambus technology has significantly improved processor access to memory in computer-based designs. This technology is based on a very high-speed, chip-to-chip interface and has been incorporated into new DRAM architectures called Rambus DRAM or RDRAM®. It can also be used with conventional processors and controllers to achieve a performance rate that is over 10 times faster than conventional DRAMs. Although Rambus systems eliminate the memory access bottleneck, they operate at the fringes of digital performance capability. The Rambus Channel transfers data on each edge of a 400-MHz differential clock to achieve an 800-MB/s data rate. Moreover, the data, clock and control lines have 800-mV logic levels that must operate in a strictly controlled impedance environment and meet specific high-speed timing requirements.
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