Next generation digital interface standards (serial, memory, display etc.) are pushing the limits of today’s compliance and debug tools posing several high speed Tx and Rx design challenges including -
Tektronix provides automated measurement suites that speed up PHY validation cycles and ensure consistency. Speed up debugging with tools like Protocol Decoding and Visual Trigger when compliance measurements fail. Identify jitter & noise from sources such as crosstalk or other multi-lane noise coupling.
|PCI Express||SATA / SAS|
|MOST||Jitter Measurement and Timing Analysis|
|Signal Integrity||Serial Data Link Analysis|
This 24-page primer offers straightforward, practical techniques for making timing jitter measurements without the need for complex statistical calculations.
This application note discusses different ways that information from an eye diagram can be sliced to gain more insight. It also discusses some basic ways that transmitters, channels, and receivers are tested.
This FREE e-Guide will help you learn more about design challenges for testing PCIe 4.0, SAS, SuperSpeed USB, and DDR4 standards. You get quick access to technical resources that will help you understand design challenges and pick the right solution for your test needs.