The BERTScope Digital Pre-emphasis Processor DPP Series takes in single-ended inputs of data and clock and condition the signal by adding controllable amounts of pre-emphasis for use with Bit Error Rate Testers.
|1 to 12.5 Gb/s range of operation, with std. 3 tap configuration||High data rate support of hardware based equalization enables compliance testing for today’s 2nd and 3rd Generation Serial Standards.|
|3-Tap equalization evaluation on 8b/10b signaling greater than 5 Gb/sec (4-tap optional)||Supports compliance tests for 802.3ap, Serial Attached SCSI, 10GBASE-KR backplanes, DisplayPort™, USB 3.0 PCI Express® Gen 3.|
|Flexible cursor position||Pre-cursor or post-cursor adjustment for optimized compensation of ISI and loss.|
|Simple interface control||Adjust tap weights directly or in a step response mapping view. Additionally a frequency domain Bode plot is provided to show effect of changes.|
|Flexible control and integration||DPP can operate as a standalone instrument controlled by a remote PC, or with a BERTScope for complete software integration. It can be precisely controlled for Backplane ISI, etc.|
|Integrated reference clock multiplication & clock doubler||For Compliance test of PCIe clock rates of 2.5 GHz, 5 GHz, 8 GHz and support for SAS-12.|
|Integrated eye opener functionality||For testing devices under test with long channels.|
PCI Express® Transmitter PLL Testing — A Comparison of Methods
Overview of significant methods for performing PLL Testing
BERTScope® DPP Series Digital Pre-emphasis Processor Fact Sheet
Key Specs and Ordering Information for BERTScope DPP Series Digital Pre-emphasis Processor
BERTScope Content Archive
Request copies of historical content from SyntheSys Research (now Tektronix Inc.) related to BERTScope.