BERTScope® Bit Error Rate Tester

The Confidence of a BERT with the Insight of an Oscilloscope

The BERTScope™ Bit Error Rate Tester Series provides a new approach to signal integrity measurements of serial data systems. Perform bit error ratio detection more quickly, accurately and thoroughly by bridging eye diagram analysis with BER pattern generation. The BERTScope™ Bit Error Rate Tester Series enables you to easily isolate problematic bit and pattern sequences, then analyze further with seven types of advanced error analysis that deliver unprecedented statistical measurement depth.

Models in the BERTScope® Bit Error Rate Tester Series: 

Model Description Max Bit Rate List Price Configure and Quote
BSA85C Bit Error Ratio Analyzer 8.5 Gb/s $146,000 Configure & Quote
BSA125C Bit Error Ratio Analyzer 12.5 Gb/s $198,000 Configure & Quote
BSA175C Bit Error Ratio Analyzer 17.5 Gb/s $237,000 Configure & Quote
BSA286C Bit Error Ratio Analyzer 28.6 Gb/s $347,000 Configure & Quote



Pattern Generation and Error Analysis, highspeed BER Measurements up to 28.6 Gb/sec.The combination of generation and analysis in one instrument enables receiver BER compliance testing for today's 3rd Generation Serial and IEEE802.3ba, 32GFC Communications Standards.
Integrated Stress Generator for stressed eye sensitivity (SRS) and jitter tolerance compliance testing.A test signal's data rate, applied stress, and data pattern can be changed on the fly, independent of each other; enabling a diverse set of signal variations for testing chipset/system sensitivity.
Integrated, BER correlated eye diagram analysis with pass/fail masks for PCI Express, USB, SATA and other communications standards.Enhances the debug experience unlike other BERT's by providing a familiar eye diagram of the test results to compare against a standards specific mask.
Error Location and BER contour analysis on PRBS 31 and other digital signals up to 28.6 Gb/sec.Provides a quick understanding of signal integrity in terms of BER. Error location provides detailed BER pattern sensitivities to speed up identification of deterministic vs. random BER errors.
Optional Jitter Map provides fast jitter decomposition, accurate stress calibration at the DUT input.Fast, effective method for determining long pattern PRBS31 jitter composition with triangulation. Graphical representation makes jitter analysis more thorough, yet simpler to follow.
Optional Digital Pre-emphasis Processor provides user controlled pre-emphasis on pattern generator supplied data.Enables testing with compliant signals for standards like PCI Express, 10GBASE-KR, SATA, 40GBASE-KR4, 100GBASE-CAUI.
Optional Clock Recovery Units provide clock recovery up to 28.6 Gb/s.Enables compliant testing and accurate Eye Pattern Analysis for high-speed serial and communication system standards.


Datasheet Accessory Description
BARACK BA-Rack Mount Kits
BSA12500ISI Differential ISI Board
View Datasheet BSAITS125

Interference Test Set with interference insertion and ISI switching

BSARACK BSA-Rack Mount Kits
BSASWITCH Hardware switch for receiver testing in applications such as USB3 compliance testing allowing attainment of loopback
PMCABLE1M Precision Phase Matched Cable Pair, 1m

Clock Recovery’s Impact on Test and Measurement

This application note discusses the outside influences that can disturb the relationship between data and how it is clocked.

Dual-Dirac+ Scope Histograms and BERTScan Measurements

Introduction to Dual-Dirac.

Anatomy of an Eye Diagram

Description of an eye diagram, how it is constructed, and common method for generating one.

Six Sigma’ Mask Testing with a BERTScope® Bit Error Rate Tester

Using Six Sigma for citical insight.

Comparing Jitter Using a BERTScope® Bit Error Rate Testing

Comparison of DCD and F/2 Jitter.

Evaluating Stress Components using BER-Based Jitter Measurements

Self-verified jitter measurements using a BER-based Jitter Peak measurement.

Bridging the Gap Between BER and Eye Diagrams — A BER Contour Tutorial

Introduction to the BER Contour measurement.

BERTScope® Bit Error Rate Testers Jitter Map “Under the Hood”

A New Methodology for Jitter Separation

PCI Express® Transmitter PLL Testing — A Comparison of Methods

Overview of significant methods for performing PLL Testing

Stressed Eye: “Know What You’re Really Testing With”

Using BER-based analysis to improve stress calibration measurements.


PCI Express 3.0 Physical Layer Testing

This webinar will explain how to prepare for PCI Express 3.0 test verification and introduce new approaches to automate transmitter and receiver tests for PCI-SIG compliance.

Automating DisplayPort Compliance Measurements

This webinar will provide engineers with an update on DisplayPort Serial Bus technology and recommended measurement approaches for compliance testing.

Verification and Compliance Testing of 10Gb/sec Thunderbolt Designs

Learn about the Thunderbotl technology, tests and challenges, and how Tektronix supports this emerging technology

Receiver Testing to Third Generation Standards Webinar

With the advent of 3rd Generation Serial Standards at rates above 5 GT/sec, it is critically important to characterize receiver performance for a successful serial communication system design. This seminar, using PCI Express 3.0 and USB3 as example standards, will highlight the latest trends and illustrate important practical learnings for successful test execution.

How to Choose the Right Platform for Jitter Measurements

Learn what to consider when selecting a platform for jitter measurements.

Beyond Receiver Interoperability Testing Webinar

This 45 minute, live webinar will focus on the latest tools and techniques for properly performing jitter tolerance and stressed receiver sensitivity testing - including characterization and margin testing of next generation receivers. .

BERTScope® Bit Error Rate Tester Related Information

Get your FREE Eye Diagram and Clock Recovery Posters

Get Your FREE Eye Diagram and Clock Recovery PostersThese posters are about testing digital high speed communications electronics, and are intended for electronics engineers who work to verify compliance of their products.

PHY Layer Testing for 100G

PHY Layer Testing for 100GIn this application note, learn how to prepare for compliance measurements on 100G standards including IEEE802.3ba and the tests that help diagnose noncompliant components and systems.

Providing Insight & Expertise for 100G Testing

Optical Communications 100G Testing SolutionsTesting 100G designs can be daunting. Learn how our solutions and expertise provide a deeper level of insight when designs fail.

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