Bit Error Rate Tester

Bridging the Information Gap

Each Tektronix Bit Error Rate Tester delivers unprecedented flexibility and performance to help compress your product development cycles and reduce verification testing costs. Quickly and confidently identify errors in digital bit streams with these highly advanced test and measurement instruments.

BERTScope® BSA Series Bit Error Rate Testers

A new approach to signal integrity measurements of serial data systems, combining the confidence of a BERT and the insight of an Oscilloscope.

BERTScope® CR Series Clock Recovery Instruments

The flexibility and accuracy you need for compliance measurements in conjunction with Bit Error Rate Testers and Sampling Oscilloscopes.

BERTScope® DPP Series Digital Pre-emphasis

Processor takes in single-ended inputs of data and clock and condition the signal by adding controllable amounts of pre-emphasis for use with a Bit Error Rate Tester.

BitAlyzer® BA Series Bit Error Rate Testers

Addressing signal integrity and BER issues faced by designers of sophisticated electronic and satellite communication system designs.

PPG3000 Series Programmable Pattern Generators

Capable of four simultaneous lanes of up to 32Gb/sec PRBS or custom digital pattern generation.

PED3000 Series Programmable Error Detectors

Provides up to 32 Gb/sec performance suitable for multi-channel, full rate error detection.

Title
Physical Layer Tests of 100 Gb/s Communications Systems Learn how to prepare for compliance measurements on 100G standards.
USB 3.0 Receiver Compliance Testing All aspects of USB 3.0 receiver testing are covered, including stressed eye calibration and jitter tolerance testing with measured device margin.
BERTScope® Bit Error Rate Testers Jitter Map “Under the Hood” A New Methodology for Jitter Separation
Bridging the Gap Between BER and Eye Diagrams — A BER Contour Tutorial Introduction to the BER Contour measurement.
Comparing Jitter Using a BERTScope® Bit Error Rate Testing Comparison of DCD and F/2 Jitter.
Evaluating Stress Components using BER-Based Jitter Measurements Self-verified jitter measurements using a BER-based Jitter Peak measurement.
PCI Express® Transmitter PLL Testing — A Comparison of Methods Overview of significant methods for performing PLL Testing
Stressed Eye: “Know What You’re Really Testing With” Using BER-based analysis to improve stress calibration measurements.
Six Sigma’ Mask Testing with a BERTScope® Bit Error Rate Tester Using Six Sigma for citical insight.
BERTScope® DPP Series Digital Pre-emphasis Processor Fact Sheet Key Specs and Ordering Information for BERTScope DPP Series Digital Pre-emphasis Processor

Title
Receiver Testing to Third Generation Standards Webinar With the advent of 3rd Generation Serial Standards at rates above 5 GT/sec, it is critically important to characterize receiver performance for a successful serial communication system design. This seminar, using PCI Express 3.0 and USB3 as example standards, will highlight the latest trends and illustrate important practical learnings for successful test execution.
How to Choose the Right Platform for Jitter Measurements Learn what to consider when selecting a platform for jitter measurements.
Beyond Receiver Interoperability Testing Webinar This 45 minute, live webinar will focus on the latest tools and techniques for properly performing jitter tolerance and stressed receiver sensitivity testing - including characterization and margin testing of next generation receivers. .