4200 CV ApplicationsGuide_Repaired

C-V Testing for

Components and

Semiconductor Devices

APPLICATIONS GUIDE

C-V Testing for Components and Semiconductor Devices

Capacitance-Voltage (C-V) testing is widely used to determine a variety of semiconductor

parameters, such as doping concentration and profiles, carrier lifetime, oxide thickness, interface

trap density, and more. This C-V testing applications guide features a collection of application notes

focused on C-V testing methods and techniques using the 4200A-SCS Parameter Analyzer. The

4200A-SCS provides three C-V methods: Multi-frequency C-V (1 kHz - 10 MHz), Very Low Frequency

C-V (10 mHz - 10 Hz,) and Quasi-static C-V measurements.

Contents

C-V Testing for Components and Semiconductor Devices

Making Optimal Capacitance and AC Impedance

Measurements with the 4200A-SCS Parameter Analyzer

C-V Characterization of MOS Capacitors

Switching Between C-V and I-V Measurements

Making Femtofarad (1e-15F) Capacitance Measurements

Automating High and Low Frequency C-V Measurements and

Interface Trap Density (DIT) Calculations of MOS Capacitors

Making Three-Terminal Capacitance-Voltage Measurements

Up to 400 V

Forced Current Quasistatic C-V Method for SiC Devices

Performing Very Low Frequency Capacitance-Voltage

Measurements on High Impedance Devices

100

Electrical Characterization of Carbon Nanotube Transistors

(CNT FETs)

111

DC I-V and AC Impedance Testing of Organic FETs

118

Electrical Characterization of Photovoltaic Materials and

Solar Cells

Making Optimal Capacitance

and AC Impedance

Measurements with the

4200A-SCS Parameter Analyzer

Making Optimal Capacitance and AC Impedance Measurements

with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

These tools, along with using proper cabling and C-V

Introduction

measurement techniques, allow the user to make highly

Capacitance-voltage (C-V) and AC impedance

sensitive capacitance measurements.

measurements are commonly performed on many types

of devices for a wide variety of applications. For example,

This application note describes how to make optimal

C-V measurements are used to determine these device

capacitance measurements using proper measurement

parameters:

techniques and the CVU Capacitance Voltage Unit.

• Gate oxide capacitance of MOSCAPs

CVU Measurement Overview

• MOSFET input and output capacitance

Figure 2 shows a simplified model of the 4210-CVU and

• Built-in potential of solar cell

4215-CVU. The capacitance of a device is determined by

• Majority carrier concentration of a diode

sourcing an AC voltage and measuring AC current and phase

• Capacitance between terminals of a BJT

while a DC voltage is applied or swept across the device.

• Oxide thickness, doping density, and threshold voltage

from a MIS capacitor

CVU

Both the 4215-CVU and 4210-CVU are multi-frequency (1 kHz

HCUR

to 10 MHz) AC impedance measurement modules for the

Source

4200A-SCS Parameter Analyzer (see Figure 1) that enables

HPOT

the user to make C-V measurements easily.The differences

between the two CVUs are the number of test frequencies

Voltmeter

DUT

and the AC drive voltage. The 4215-CVU has 10,000 discreet

LPOT

frequencies with 1 kHz resolution and the 4210-CVU has

I_DUT

37 discreet frequencies. The AC drive voltage range of the

LCUR

4215-CVU is 10 mV to 1 V rms and the range of the 4210-CVU

Ammeter

is 10 mV to 100 mV rms.

Figure 2. Simplified CVU diagram

The time domain AC values are processed into the

frequency domain to produce the phasor form of the

impedance. The device capacitance is calculated from the

AC impedance and the test frequency using this equation:

I_DUT

_______

DUT

2πfV_ac

The CVU measures capacitance using the auto-balance

Figure 1. 4200A-SCS Parameter Analyzer

bridge (ABB) method. The ABB is used to nullify an AC

signal of known frequency on one terminal (LPOT if the

The CVUs are designed with unique circuitry and are

AC ammeter is on LCUR) of a DUT to guard out stray

controlled by the Clarius software to support features

impedances. This AC ground keeps the LPOT terminal

and diagnostic tools that ensure the most accurate

of the CVU at 0 VAC, so that all the AC current in the test

results. Some of the CVU’s built-in tools include real-time

circuit flows to the AC ammeter and not through any parallel

measurement mode, open/short compensation, parameter

capacitances in the test circuit.

extraction formulator, filtering, timing controls, and the

ability to switch the AC ammeter terminal in the software.

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Making Optimal Capacitance and AC Impedance Measurements

with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Depending on the test settings, which include

the frequency, AC drive voltage, and current

range, the CVU can measure capacitances in

the sub-picofarad to millifarad ranges. The

user-specified test frequency depends on the

device being tested and the parameters being

derived. The range of test frequencies is from

1 kHz to 10 MHz. The DC bias function is ±30 V

(60 V differential).

Figure 3. Simplified measurement models

Measurement Models and

Parameters

Z = Impedance

Typical models of a measurement DUT

θ = Phase Angle

are usually a series or parallel resistance-

R = Resistance

X = Reactance

capacitance (RC) circuit. As shown in the

Y = Admittance

simplified models in Figure 3, the CVU can

G = Conductance

B = Susceptance

measure the DUT as a series configuration

(R_SC_S) or as a parallel configuration (R_PC_P).

Figure 4. Vector Diagram for Impedance

The CVU can measure and display these

parameters:

Measuring Instrument

Signal Path

Device and Fixturing

Including Software

(Cables, Switch Matrix)

(Chuck, Prober, Test Box)

• Impedance and phase angle (Z, Theta)

(CVU)

• Resistance and reactance (R+jX)

HCUR

Source

CVH

• Parallel capacitance and conductance

HPOT

(C_P-G_P)

DUT

Voltmeter

• Series capacitance and resistance (C_S-R_S)

LPOT

LCUR

CVL

• Parallel capacitance and dissipation factor

Ammeter

(C_P-D)

• Series capacitance and dissipation factor

(C_S-D)

Figure 5. C-V measurement system

• Admittance and phase angle (Y, theta)

By using the built-in Formulator tool in Clarius, other parameters such as

inductance can be easily extracted from the measured data. The vector

diagram for Impedance in Figure 4 shows the fundamental equations for

impedance.

AC Impedance Measurement System

A C-V measurement system, as shown in Figure 5, can be quite complicated

because the configuration includes the measuring instrument and software,

the cabling of the signal path, test fixturing, and the device. To make optimal

measurements, the test settings and timing parameters of the CVU need to be

set appropriately. Proper cabling, probers, and test fixtures must be used, and

then connection compensation must be performed. Finally, the device itself

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Making Optimal Capacitance and AC Impedance Measurements

with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

can cause problem measurements. The next few sections

An example of four-wire sensing to the DUT is shown in

will discuss hardware and software considerations for

Figure 7. In this case, the HCUR and HPOT terminals are

making good capacitance measurements.

connected to one end of the device, and the LPOT and

LCUR terminals are connected to the other end of the

device. To improve the bandwidth, connect the outside

Cabling and Connections

shields of the coax cables to the metal test fixture. Use

This section describes using the proper cabling and

four-wire connections to the device to facilitate sensitive

connections, AC guarding of the chuck and device

measurements by sensing the voltage as close as possible

terminals, and configuring the AC ammeter terminal.

to the device. The outside shields of each of the four coax

cables must be connected as close as possible to the device

Proper Cabling

to minimize the loop area of the shields. The outside shields

of the coax cables also get connected to the metal test

For the best measurement results, use only the supplied

fixture to reduce noise and coupling from external sources.

red SMA cables for making connections to the CVU. The

This reduces the inductance and helps to avoid resonance

following accessories are supplied:

effects, which can be burdensome at frequencies higher

(4) CA-447A SMA to SMA 1.5 m cables (red)

than 1 MHz.

(4) CS-1247 SMA to BNC Adaptors

(2) CS-701A BNC Tees

(1) Torque wrench to tighten SMA cable connections

The supplied accessories allow connecting to a test fixture

or prober with BNC or SMA connections. The CVU, as well as

the supplied accessories configured for two-wire sensing,

are shown in Figure 6. A CS-1247 SMA-to-BNC Adaptor is

connected to each CA-447A SMA-to-SMA Cable. HCUR and

HPOT terminals are connected by a CS-701A BNC tee to form

Figure 7. Proper connections from the CVU to a DUT

CVH, and LCUR and LPOT are connected together to form

CVL. Using the supplied torque wrench, tighten the SMA

Figure 8 shows a ground jumper connecting the commons

cable connections to ensure good contacts. The red SMA

of two prober cable assemblies. Keithley Instruments has

cables are 100 Ω. Two 100 Ω cables in parallel are 50 Ω, which

a series of 4210-MMPC Multi-Measurement Cable Kits for

is standard for high frequency sourcing and measuring

various probers that enable the common connections of

applications.

various manipulators.

Figure 6. CVU connections for two-wire sensing

Figure 8. Ground jumper connecting the commons of two manipulators

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Making Optimal Capacitance and AC Impedance Measurements

with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

In general, proper cabling is crucial to making successful

Guarding Device Terminals

capacitance measurements. Here are some potential

To measure the capacitance between two terminals on

cabling problems:

a device with three or more terminals, it is important to

• Mismatched length on different CVU terminals

guard the third terminal to prevent unwanted capacitances

from affecting the measurement accuracy. This is best

• Improper cable impedance (not using red SMA cables)

illustrated through an example. As shown in Figure 10, the

• Shield connections of all the cables not connected or

CVU is connected to measure the capacitance between the

not connected close enough to the DUT

Base and Emitter (C_BE) of a BJT.

• Bent, crimped or flattened cables

• SMA cable connectors not making good contact

Collector

C_BC

• Not choosing the proper cable length in the Configure

CVU

view of the Clarius software

HCUR

(AC V)

Base

CCE

HPOT

Guarding the Chuck

LPOT

Guarding can reduce the effects of parallel impedance,

C_BE

or stray capacitance, on capacitance measurement

LCUR

Emitter

(AC ammeter)

accuracy. The guard terminal is the outside shield of the

coax connectors of the CVU. This guard terminal of the

Figure 10. Measuring the base-emitter capacitance (CBE)

CVU should not be confused with the 4200A-SCS’s GNDU

terminal, which is connected to chassis ground.

However, the series combination of capacitance between

the other terminals (C_BC and C_CE) is in parallel with C_BE and

When making C-V measurements between two terminals on

creates an AC leakage path that can lead to erroneous

the top of the wafer, it may be necessary to guard the chuck

readings. This parallel capacitance from the other terminals

to reduce parallel capacitance between the terminals of

will affect the measurement (C_MEAS) as follows:

the DUT and the chuck. In Figure 9, the stray capacitance

C_BC · C_CE

is reduced by connecting the guard, the shields of the coax

___________

C_MEAS = C_BE +

(

C_BC + C_CE

)

cables, to the chuck. For C-V measurements on devices

that use the backside of the wafer as a contact, such as is

To prevent the stray capacitance from affecting the

the case for MOSCAPs, the chuck cannot be connected to

measurement accuracy, the Collector is guarded by

guard.

connecting it to the outside shield of the coax cable, which

is at 0 VAC. This is illustrated in Figure 11. This AC guard

routes the leakage capacitance current away from the AC

LCUR

LPOT

HPOT

HCUR

CVU

current measurement terminal (LCUR), so that only the AC

is measured.

current due to C_BE

Connect Shields

of Cables to Chuck

To Guard Stray

Capacitance from

Guard Connection

0V AC

Capacitance

the Wafer to the

from DUT

CDUT on Wafer

Chuck

Collector

Terminal to

C_BC

Chuck

CVU

Figure 9. Connecting the CVU guard to the chuck

HCUR

Base

(AC V)

C_CE

HPOT

LPOT

C_BE

LCUR

Emitter

(AC ammeter)

Figure 11. Guarded C-V measurement of BJT

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Making Optimal Capacitance and AC Impedance Measurements

with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

The Clarius software allows users to change the output of

Using the 4200A-CVIV Multi-Switch to

the 4200A-CVIV automatically so that any of the terminals

Guard Device Terminals

of the device can be guarded. Figure 14 shows the CVIV

Guarded C-V measurements can be automated using the

Multi-Switch Channel Config settings in Clarius.

optional 4200A-CVIV Multi-Switch, shown in Figure 12. The

CVIV enables the user to switch automatically between I-V

(SMU) and C-V (CVU) measurements on a device, as well as

connect C-V guard to any terminal on the DUT.

Figure 14. cviv-configure settings for base-emitter capacitance

measurements on a BJT

AC Ammeter Connections

Figure 12. 4200A-CVIV Multi-Switch

By default, the LCUR terminal of the CVU is the AC Ammeter

Figure 13 shows the CVHI, CVLO, and CV Guard terminals

connection, and the HCUR terminal is the AC Source Voltage

of the CVU connected to the three terminals of the BJT

terminal (as shown in Figure 2). However, users have

through the outputs of the 4200A-CVIV. In this example, the

the option to change the function of the terminals in the

CV Guard is switched through Channel 3 of the 4200A-CVIV

Advanced Terminal Settings window in the Clarius software

to the collector terminal of the BJT so that the base-emitter

as shown in Figure 15. Without the need to change cables

capacitance can be measured between CVHI and CVLO.

manually, lift the prober needles, or physically change the

test setup, it’s easy to eliminate potential measurement

problems by changing the terminal settings in the software.

4200A-CVIV

2-Wire Mode

Sense

Channel 4

OPEN

Force

Sense

Channel 3

CV GUARD

Guarded

Force

Sense

Channel 2

CV HI

Iac

Force

Sense

Channel 1

Vac

C_be

CV LO

Force

Figure 13. Connections from the 4200A-CVIV to a BJT for guarded

Figure 15. Advanced terminals settings

measurements

This feature allows measuring the AC current on the

least noisy terminal, which will provide a more useful

measurement. It’s also possible to change the terminal

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Making Optimal Capacitance and AC Impedance Measurements

with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

to which the DC voltage is applied. The DC voltage can be

Acquire the CVU compensation data for open and

combined on the same terminal as the AC ammeter, which is

short corrections. To perform the corrections in

ideal for connections to the gate of a MOS capacitor.

Clarius, select Tools and then select CVU Connection

Compensation. Select Measure Open or Measure Short.

To avoid noisy measurements and stray capacitance, always

When compensation data is acquired, it is taken at all

connect the AC ammeter terminal to the terminal of the

test frequencies.

device that has the least amount of capacitance to ground.

2. Enable the correction on the Terminal Settings pane of a

In the example shown in Figure 16, the LCUR (AC ammeter)

CVU test.

connection is made to Pad 1 because it has less parasitic

capacitance to common than Pad 2. In many cases, the

Open Correction

user will not know which pad has the least capacitance to

ground, but it’s easy to check by reversing the HCUR and

Open correction is an offset correction for measuring small

LCUR leads in the Advanced Terminal Settings tab and

capacitances or high impedances. Probes must be up or the

seeing if that produces better results.

device removed from the test fixture during the correction.

The outside shields of the cables must be tied together

during the open correction, as shown in Figure 17.

CVU

HCUR

(DC Vsource)

HPO T

LPO T

LCUR

DUT

(ammeter)

Pad

C₁, C₂ = Parasitic

Capacitance to

Common

Figure 16. CVU measurements with parasitic capacitance to common

Connection Compensation

Figure 17. Connections for open connection compensation for the 4210-CVU

and 4215-CVU

The CVU is designed to be connected to a prober or test

fixture via interconnect cables and adaptors and may be

An example that shows the effects of Open Compensation

possibly routed through a 4200A-CVIV Multi-Switch or

is illustrated in the C-V curves for a MOSFET in Figure 18.

switch matrix to the DUT. This cabling and switch matrix

These graphs show the C-V sweeps between the gate and

will add parasitic inductance and stray capacitance to the

the drain/source/bulk tied together generated with and

measurements. To correct for offset errors caused by

without Open Compensation. The purple curve is without

these connections, the Clarius software has a built-in tool

compensation and the blue curve is with compensation. The

to perform compensation. Connection Compensation is a

difference between the two curves is about 0.23 pF.

two-part process:

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Making Optimal Capacitance and AC Impedance Measurements

with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Quiet Readings

• Use the Speed mode settings to adjust the

measurement window. The longer the measurement

time, or window, the less noisy measurements will be.

First, try using the Quiet speed mode. If necessary,

use the Custom speed which enables the user to set

the time of the measurement window. The time of the

measurement window can be calculated as follows:

Measurement Window = (A/D Aperture Time) *

(FilterFactor2 or Filter Count)

• Further information on making very sensitive

capacitance measurements can be found in the Keithley

Instruments application note, “Making Femtofarad

(1e-15f) Capacitance Measurements with the 4215-CVU

Figure 18. C-V measurements on a MOSFET with and without

Capacitance Voltage Unit.”

Open Compensation

Settled Readings

Short Correction

• Sweep Delay time allows the device to charge up to

equilibrium before taking a measurement.

Short correction is an offset correct for large capacitance,

low impedance, and inductance measurements. Short

• Apply a bias voltage for a specified Hold Time at the

compensation removes the effect of offsets caused by

beginning of a sweep to allow the device to charge up to

series resistance and parasitic inductance. Connect a short

the first voltage step of the sweep prior to the start of

between all the output terminals, keeping the shields tied

the sweep.

together. Use a BNC or SMA barrel to connect the cables

together or short the probes together on a metal contact.

Timing Settings

To make successful C-V measurements, it’s important to

choose the appropriate timing parameters in the Clarius

software. Adjustments to timing parameters can help

prevent noisy measurements and allow acquiring readings

in equilibrium. Timing adjustments are made in the CVU

Advanced Test Settings window in the Configure view, which

is shown in Figure 19. The following adjustments can allow

for making quiet or settled readings:

Figure 19. CVU Advanced Test Settings window

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Making Optimal Capacitance and AC Impedance Measurements

with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Equilibrium Conditions

Dissipation Factor and Choosing the

Correct Measure Model

The condition of a device when the internal capacitance

is fully charged after an applied step voltage is referred to

One way of determining the confidence in capacitance

as the “equilibrium” condition. If C-V measurements are

measurements is to check the dissipation factor (D), which

made before the device is in equilibrium, inaccurate results

is defined as the ratio between the reactance and the

may occur. There are two ways to verify if a device is in

resistance of a simple parallel capacitance model. Here is

equilibrium:

the equation for parallel and series models:

Reactance

Check the shape of the C-V curve when sweeping

D =

___________

_________

= 2πfR_SC_S

Resistance

2πfR_PC_P

from either direction. For example, the C-V curve of

a MOSCAP should look the same from accumulation

where:

to inversion or from inversion to accumulation. For

R_P = the parallel resistance of the test device in Ω

testing MOSCAPs, further information on choosing

Hold and Sweep Delay times can be found in the

C_P = the parallel capacitance of the test device in F

Keithley application note, “C-V Characterization of MOS

Capacitors using the 4200A-SCS Parameter Analyzer.”

f = the test frequency in Hz

2. Set up a test in the Sampling mode to apply a voltage

R_S = the series resistance of the test device in Ω

bias and graph the capacitance vs. time of the device.

Observe from the graph the time it takes for the device

C_S = the series capacitance of the test device in F

to charge up. For example, the graph in Figure 20 shows

a curve of the capacitance vs. time, measured between

The parallel capacitance (C_P) and series capacitance (C_S) are

the emitter and base of a BJT. The applied voltage was

related by the following equation:

0.5 VDC. From the graph, the equilibrium time is about 13

______

C_P = C_S

seconds. Because the equilibrium time is very long for

(

1 + D²

)

this device, it may be a bad device. This is the process to

With the CVU, it’s possible to measure the dissipation factor

use to determine the equilibrium time.

by selecting the C_P-D Measure Parameter in the Advanced

Test Settings window, as shown in Figure 21.

Figure 21. Selecting the C_P-D measurement parameter

Ideally, C_P and C_S should be equal. This will occur if D=0.

Even if D is small (<0.1), there is effectively no difference

between C_P and C_S. However, if D is large (>0.1), then

it’s necessary either to determine the correct model or

Figure 20. Equilibrium time measurement example

troubleshoot the measurements.

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Making Optimal Capacitance and AC Impedance Measurements

with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

If C

and C_S are not equal and D is large, it’s possible to determine which model, series or parallel, is correct. Separately

measure C_P and C_S as a function of voltage or frequency. If either of the C-V or C-f curves are flat for C_P or C_S, then that is the

correct model (series or parallel) to use. If none of the curves are flat, then it’s necessary to troubleshoot the measurements

to figure out the source of the problem. The problem might be a leaky device, connection issues (cabling), or a device issue

such as AC leakage between the pads (may need to use AC guarding).

Troubleshooting

When troubleshooting capacitance

measurements, the CVU has built-in tools

that can help. In addition to using Cable

Compensation, adjusting the AC Ammeter

Connections, and setting the appropriate

Timing Parameters as previously discussed,

other tools in Clarius such as Confidence Check,

Real-Time Measurements, Status Codes, and

Status Indicators are available.

Confidence Check

Confidence Check is a diagnostic tool that

allows checking the integrity of open and short

connections. This is especially important if

making measurements through a switch. To

Figure 22. CVU Confidence Check Open and Short Dialog boxes

enable Confidence Check, select Tools at the

top of the Clarius screen.

To verify an open circuit, lift the probes or

remove the device from the test fixture. Select

Check Open. Follow the instructions and select

OK. When the open check is complete, the

dialog box displays the results of the test. This

process can be repeated to test for a Short after

a short is connected. If either test fails, the

results include suggestions for troubleshooting.

In the example shown in Figure 22, the Open

test passed and the Short test failed.

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Making Optimal Capacitance and AC Impedance Measurements

with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Real-Time Measurements

The CVU Real-Time Measurement Mode in the

Tools menu provides a direct, real-time user

interface to the CVU to help in system setup

and debugging. The Real-Time Measurement

window is shown in Figure 23. For example, it

can be used to confirm that contact has been

made from the CVU to the pads on a wafer.

Follow these steps to generate real-time

measurements:

• Go to the Tools menu

• Select CVU Real-Time Measurement

• Set up the desired parameter settings

• Select Run

Figure 23. Real-Time Measurements window

• Select Stop to quit taking readings.

ABB Unlock Errors

Status Indicators

The CVU uses the auto-balancing bridge (ABB) technique

The CVU status code indicates the current measurement

to achieve accurate impedance measurements. The

range, including an overflow condition, for each reading

ABB creates a virtual ground at the DUT to minimize

and flags any errors. When enabled, a data column labeled

measurement error. Every CVU measurement is made with

CVU1S will appear in the Sheet in the Analyze View. Enable

ABB active. The ABB always attempts to lock the low side of

status code by selecting Report Status, located in the

the DUT to virtual ground.

Advanced Terminal Settings tab in the Configure view.

If the ABB fails to lock, the measurement is made but may

When a measurement error occurs, the entire row of data

be out of specification. If this occurs, the returned data is

in the Sheet related to the measurement changes color.

flagged and shown in yellow on the Analyze sheet. Here are

The data values in the flagged data become color-coded, as

the common reasons that the ABB fails to lock:

shown in Figure 24, to identify the error type:

• The cable lengths connected to the CVU terminals are

• Red: Measurement Time Out

not the same

• Magenta: Measurement Overflow

• HPOT or LPOT terminals are disconnected

• Yellow: Auto-Balance Bridge (ABB) not locked

• Excessive noise in the LPOT terminal

• High frequency sources

• Physical cable lengths do not match the cable length set

in Clarius

• Improperly torqued SMA cables

• Too much parasitic noise

Figure 24. Example of flagged measurement errors appearing in the Sheet

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Making Optimal Capacitance and AC Impedance Measurements

with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Error Symptoms

Table 1 provides some troubleshooting tips for various measurement problems.

Table 1. C-V Measurement Troubleshooting Table

Error Symptoms

Possible Causes

Suggestions to Minimize or Avoid Errors

Use Open Connection Compensation, minimize stray

Cabling and connections capacitance

capacitance

Light left ON or lid open

Turn off light

Capacitance too high

Unwanted capacitance from other terminals

Use guarding

Try another DUT, use Confidence Check for verification, check if

Short or leaky device

dissipation factor <0.1

Device not in equilibrium

Increase delay or hold time

Re-verify connections and use Confidence Check to check for

Poor or no contact to device

Open. May need to improve contact between wafer and chuck.

Capacitance too low

Try another device to verify if the problem is the device or

Open device

something else. Use Confidence Check.

Coax cable shields not connected

Connect shields as close as possible to the device.

Use Quiet or Custom Speed Modes. Increase or reduce test

Environment

frequency depending on magnitude of capacitance. Verify

prober contact to device.

Noisy Measurements

CVL and CVH connections inverted

Try switching terminals in the Advanced Test Settings Window.

Enclose device in shielded test fixture that is connected to

Device not shielded

outside shields of coax cables.

Set PreSoak voltage to first voltage point in sweep and use

Device not in equilibrium

sufficient Hold Time to allow device to charge up.

“Tails” on end of C-V sweep

Try measuring the leakage current using the SMU, reduce the

Leaky device

DC voltage.

Conclusion

Good capacitance measurements can be easily achieved using the CVU’s built-in measurement tools, proper cabling and

connections, and appropriate measurement techniques. Some of the many built-in tools include compensation, timing

parameters, and confidence check.

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C-V Characterization

of MOS Capacitors

Using the 4200A-SCS

Parameter Analyzer

C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Introduction

Overview of C-V Measurement

Maintaining the quality and reliability of gate oxides of

Technique

MOS structures is a critical task in a semiconductor fab.

By definition, capacitance is the change in charge (Q) in a

Capacitance-voltage (C-V) measurements are commonly

device that occurs when it also has a change in voltage (V):

used in studying gate-oxide quality in detail. These

ΔQ

measurements are made on a two-terminal device called

C≡

a MOS capacitor (MOS cap), which is basically a MOSFET

One general practical way to implement this is to apply a

without a source and drain. C-V test results offer a wealth

small AC voltage signal (millivolt range) to the device under

of device and process information, including bulk and

test, and then measure the resulting current. Integrate the

interface charges. Many MOS device parameters, such as

current over time to derive Q and then calculate C from Q

oxide thickness, flatband voltage, threshold voltage, etc.,

and V.

can also be extracted from the C-V data.

C-V measurements in a semiconductor device are made

Using a tool such as the Keithley 4200A-SCS Parameter

using two simultaneous voltage sources: an applied AC

Analyzer equipped with the 4210-CVU or 4215-CVU

voltage signal (dV_ac) and a DC voltage (V_dc) that is swept in

Integrated C-V Option for making C-V measurements on

time, as illustrated in Figure 1.

MOS capacitors can simplify testing and analysis. The

4200A-SCS is an integrated measurement system that can

include instruments for both I-V and C-V measurements,

Vdc

as well as software, graphics, and mathematical analysis

capabilities. The software incorporates C-V tests, which

include a variety of complex formulas for extracting

common C-V parameters.

dV_ac

This application note discusses how to use a Keithley

4200A-SCS Parameter Analyzer equipped with the

4210-CVU or 4215-CVU Integrated C-V Option to make

C-V measurements on MOS capacitors. It also addresses

the basic principles of MOS caps, performing C-V

Time

measurements on MOS capacitors, extracting common C-V

parameters, and measurement techniques. The Keithley

Figure 1. AC and DC voltage of C-V Sweep Measurement

Clarius software that controls the 4200A-SCS incorporates

many tests and projects specific to C-V testing. Each

The magnitude and frequency of the AC voltage are fixed;

project is paired with the formulas necessary to extract

the magnitude of the DC voltage is swept in time. The

common C-V parameters, such as oxide capacitance, oxide

purpose of the DC voltage bias is to allow sampling of the

thickness, doping density, depletion depth, Debye length,

material at different depths in the device. The AC voltage

flatband capacitance, flatband voltage, bulk potential,

bias provides the small-signal bias so the capacitance

threshold voltage, metal-semiconductor work function

measurement can be performed at a given depth in

difference, and effective oxide charge. This completeness

the device.

is in sharp contrast to other commercially available C-V

solutions, which typically require the user to research and

enter the correct formula for each parameter manually.

WWW.TEK.COM | 17

C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

The three modes of operation, accumulation, depletion

Basic Principles of MOS Capacitors

and inversion, will now be discussed for the case of a

Figure 2 illustrates the construction of a MOS capacitor.

p-type semiconductor, then briefly discussed for an n-type

Essentially, the MOS capacitor is just an oxide placed

semiconductor at the end of this section.

between a semiconductor and a metal gate. The

semiconductor and the metal gate are the two plates of the

Accumulation Region

capacitor. The oxide functions as the dielectric. The area of

the metal gate defines the area of the capacitor.

With no voltage applied, a p-type semiconductor has

holes, or majority carriers, in the valence band. When a

Metal Gate

negative voltage is applied between the metal gate and

the semiconductor, more holes will appear in the valence

band at the oxide-semiconductor interface. This is because

Metal

the negative charge of the metal causes an equal net

Oxide

positive charge to accumulate at the interface between

Semiconductor

the semiconductor and the oxide. This state of the p-type

semiconductor is called accumulation.

Back Contact

For a p-type MOS capacitor, the oxide capacitance is

measured in the strong accumulation region. This is where

Figure 2. MOS capacitor

the voltage is negative enough that the capacitance is

essentially constant and the C-V curve is almost flat. This

The most important property of the MOS capacitor is that

is where the oxide thickness can also be extracted from the

its capacitance changes with an applied DC voltage. As a

oxide capacitance. However, for a very thin oxide, the slope

result, the modes of operation of the MOS capacitor change

of the C-V curve doesn’t flatten in accumulation and the

as a function of the applied voltage. Figure 3 illustrates

measured oxide capacitance differs from the actual oxide

a high frequency C-V curve for a p-type semiconductor

capacitance.

substrate. As a DC sweep voltage is applied to the gate, it

causes the device to pass through accumulation, depletion,

Depletion Region

and inversion regions.

When a positive voltage is applied between the gate and

the semiconductor, the majority carriers are replaced

from the semiconductor-oxide interface. This state of the

semiconductor is called depletion because the surface of

the semiconductor is depleted of majority carriers. This

area of the semiconductor acts as a dielectric because

it can no longer contain or conduct charge. In effect, it

becomes an insulator.

The total measured capacitance now becomes the oxide

capacitance and the depletion layer capacitance in series,

and as a result, the measured capacitance decreases. This

decrease in capacitance is illustrated in Figure 3 in the

depletion region. As a gate voltage increases, the depletion

region moves away from the gate, increasing the effective

thickness of the dielectric between the gate and the

substrate, thereby reducing the capacitance.

Figure 3. C-V curve of a p-type MOS capacitor measured with the CVU

18 | WWW.TEK.COM

C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Inversion Region

n-type Substrate

As the gate voltage of a p-type MOS-C increases beyond

The C-V curve for an n-type MOS capacitor is analogous

the threshold voltage, dynamic carrier generation and

to a p-type curve, except that (1) the majority carriers

recombination move toward net carrier generation. The

are electrons instead of holes; (2) the n-type C-V curve

positive gate voltage generates electron-hole pairs and

is essentially a mirror image of the p-type curve; (3)

attracts electrons (the minority carriers) toward the gate.

accumulation occurs by applying a positive voltage to the

Again, because the oxide is a good insulator, these minority

gate; and (4) the inversion region occurs at negative voltage.

carriers accumulate at the substrate-to-oxide/well-to-

oxide interface. The accumulated minority-carrier layer

Performing C-V Measurements with

is called the inversion layer because the carrier polarity

the CVU

is inverted. Above a certain positive gate voltage, most

available minority carriers are in the inversion layer, and

To simplify testing, a project has been created for the

further gate-voltage increases do not further deplete the

4200A-SCS that makes C-V measurements on a MOS

semiconductor. That is, the depletion region reaches a

capacitor and extracts common measurement parameters

maximum depth.

such as oxide thickness, flatband voltage, threshold voltage,

etc. The MOS Capacitor C-V Project (cvu-moscap) is included

Once the depletion region reaches a maximum depth,

with all 4200A-SCS systems in the Clarius application.

the capacitance that is measured by the high frequency

Figure 4 is a screen shot of the project, which has three

capacitance meter is the oxide capacitance in series with

tests that generate a C-V sweep (moscap-cvsweep), a 1/C²

the maximum depletion capacitance. This capacitance is

vs. Gate Voltage curve (moscap-c-2vsv), and a doping profile

often referred to as minimum capacitance. The C-V curve

(moscap-dopingprofile). Figure 4 also illustrates a C-V

slope is almost flat.

sweep generated with the moscap-cvsweep test. All of the

extracted C-V parameters in these test modules are defined

NOTE: The measured inversion-region capacitance at the

in the next section of this application note.

maximum depletion depth depends on the measurement

frequency. Therefore, C-V curves measured at different

frequencies may have different appearances. Generally,

such differences are more significant at lower frequencies

and less significant at higher frequencies.

WWW.TEK.COM | 19

C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Figure 4. C-V sweep created with moscap-cvsweep test for the 4200A.

20 | WWW.TEK.COM

C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

MOS Capacitor C-V Sweep (moscap-cvsweep) Test

This test performs a capacitance measurement at each step of a user-configured linear voltage sweep. A C-V graph is

generated from the acquired data, and several device parameters are calculated using the Formulator, which is a tool in the

4200A-SCS’s software that provides a variety of computational functions, common mathematical operators, and common

constants. Figure 5 shows the window of the Formulator. These derived parameters are listed in the Analyze view of the test.

Figure 5. Formulator window with parameters derived

MOS Capacitor I/C² vs. Gate Voltage Sweep

(moscap-c-2vsv) Test

This test performs a C-V sweep and displays the

capacitance (1/C²) as a function of the gate voltage (V_G).

This sweep can yield important information about doping

profile because the substrate doping concentration (N_SUB)

is inversely related to the reciprocal of the slope of the

1/C² vs. V_G curve. A positive slope indicates acceptors and

a negative slope indicates donors. The substrate doping

concentration is extracted from the slope of the 1/C² curve

and is displayed on the graph. Figure 6 shows the results of

executing this test module.

Figure 6. 1/C² vs. gate voltage plot generated with the CVU

WWW.TEK.COM | 21

C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

MOS Capacitor Doping Profile

Measurement Optimization

(moscap-dopingprofile) Test

Successful measurements require compensating for stray

This test performs a doping profile, which is a plot of the

capacitance, measuring at equilibrium conditions, and

doping concentration vs. depletion depth. The difference in

compensating for series resistance.

capacitance at each step of the gate voltage is proportional

to the doping concentration. The depletion depth is

Offset Correction for Stray Capacitance

computed from the high frequency capacitance and oxide

capacitance at each measured value of the gate voltage.

C-V measurements on a MOS capacitor are typically

The results are plotted on the graph as shown in Figure 7.

performed on a wafer using a prober. The CVU is designed

to be connected to the prober via interconnect cables and

adaptors and may possibly be routed through a switch

matrix. This cabling and switch matrix will add stray

capacitance to the measurements.

To correct for stray capacitance, the Clarius software

has a built-in tool for offset correction, which is a two-

part process: the corrections for open and/or short are

performed first, and then they can be enabled within a test.

To perform the corrections, select Tools and select CVU

Connection Compensation. For an Open correction, select

Measure Open. Probes must be up during the correction.

Open is typically used for high impedance measurements

(<10pF or >1MΩ).

For a Short correction, select Measure Short. Short

Figure 7. Doping profile extracted from C-V data taken with the CVU

the probe to the chuck. A short correction is generally

performed for low impedance measurements (>10nF

or <10Ω).

Connections to the CVU

To make a C-V measurement, a MOS cap is connected to the

After the corrections are performed, they must be enabled

CVU as shown in Figure 8. In the test, both the CVU ammeter

in the test. To enable corrections, select the CVU Open

and the DC voltage appear at the HCUR/HPOT terminals. See

and/or Short checkboxes in the Terminal Settings pane

the next section, “Measurement Optimization,” for further

(Figure 9).

information on connecting the CVU to the device on a wafer.

HICUR

HIPOT

Wafer

Gate

CVU

Bulk

LPOT

LCUR

Figure 8. Basic configuration to test MOS capacitor with the CVU

22 | WWW.TEK.COM

C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Figure 9. CVU compensation window

Measuring at Equilibrium Conditions

Hold and Delay Times When Sweeping from Inversion →

Accumulation. When the C-V sweep starts in the inversion

A MOS capacitor takes time to become fully charged after a

region and the starting voltage is initially applied, a MOS

voltage step is applied. C-V measurement data should only

capacitor is driven into deep depletion. Thereafter, if the

be recorded after the device is fully charged. This condition

starting voltage is maintained, the initial high frequency

is called the equilibrium condition. Therefore, to allow the

C-V curve climbs toward and ultimately stabilizes to the

MOS capacitor to reach equilibrium: (1) allow a sufficient

minimum capacitance at equilibrium. However, if the

Hold Time in the Test Settings panel to enable the MOS

initial Hold Time is too short, the MOS capacitor cannot

capacitor to charge up while applying a “PreSoak” voltage,

adequately recover from deep depletion, and the measured

and (2) allow a sufficient Sweep Delay Time before recording

capacitance will be smaller than the minimum capacitance

the capacitance after each voltage step of a voltage sweep.

at equilibrium. Set the “PreSoak” voltage to the first voltage

The appropriate Hold and Delay Times are determined

in the voltage sweep and allow a sufficient Hold Time for the

experimentally by generating capacitance vs. time plots and

MOS capacitor to reach equilibrium.

observing the time for the capacitance to settle.

However, once the MOS capacitor has reached equilibrium

Although C-V curves swept from different directions

after applying the “PreSoak” voltage, an inversion →

may look different, allowing adequate Hold and Delay

accumulation C-V sweep may be performed with small

Times minimizes such differences. One way to determine

delay times. This is possible because minority carriers

sufficient Hold and Delay Times is to generate a series of

recombine relatively quickly as the gate voltage is reduced.

C-V curves in both directions. Change the Hold and Delay

Nonetheless, if the Delay Time is too short, non-equilibrium

Times for each pair of inversion → accumulation and

occurs, and the capacitance in the inversion region is

accumulation → inversion curves until the curves look

slightly higher than the equilibrium value. This is illustrated

essentially the same for both sweep directions.

by the upper dotted line in Figure 10.

WWW.TEK.COM | 23

C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

a sudden voltage change when the sweep starts. During

biasing, if necessary, a short light pulse can be applied to

the sample to help generate minority carriers. However,

before the sweep starts, all lights should be turned off.

All measurements should be performed in total darkness

Swept too fast

because the semiconductor material may be light sensitive.

During the sweep, the Delay Time should be chosen to

create the optimal balance between measurement speed

Equilibrium

sweep

and measurement integrity, which requires adequate

V_GS

equilibration time.

Figure 10. Effects of performing a C-V sweep too quickly

Compensating for series resistance

Hold and Delay Times When Sweeping from Accumulation

After generating a C-V curve, it may be necessary to

→ Inversion. When the C-V sweep starts in the

compensate for series resistance in measurements. The

accumulation region, the effects of Hold and Delay Times

series resistance (R_SERIES) can be attributed to either the

in the accumulation and depletion regions are fairly subtle.

substrate (well) or the backside of the wafer. For wafers

However, in the inversion region, if the Delay Time is too

typically produced in fabs, the substrate bulk resistance

small (i.e., the sweep time is too fast), there’s not enough

is fairly small (<10Ω) and has negligible impact on C-V

time for the MOS capacitor to generate minority carriers to

measurements. However, if the backside of the wafer is

form an inversion layer. On the high frequency C-V curve, the

used as an electrical contact, the series resistance due

MOS capacitor never achieves equilibrium and eventually

to oxides can significantly distort a measured C-V curve.

becomes deeply depleted. The measured capacitance

Without series compensation, the measured capacitance

values fall well below the equilibrium minimum value. The

can be lower than the expected capacitance, and C-V curves

lower dotted line in Figure 10 illustrates this phenomenon.

can be distorted. Tests for this project compensate for

series resistance using the simplified three-element shown

Using the preferred sequence. Generating a C-V curve by

in Figure 12. In this model, C_OX is the oxide capacitance and

sweeping from inversion to accumulation is faster and more

C_A is the capacitance of the accumulation layer. The series

controllable than sweeping from accumulation to inversion.

resistance is represented by R_SERIES.

Figure 11 illustrates a preferred measurement sequence.

Bias

Hold Time

C_A

Bias

Start Voltage

Voltage

C_OX

Simplifies to

Delay

Time

R_SERIES

Light

SERIES

0 V

Pulse

Figure 11. Preferred C-V measurement Sequence

Equivalent 3-element

Simplified model used

model of MOS capacitor

to determine R_SERIES

in strong accumulation

The device is first biased at the “PreSoak” voltage for

the specified Hold Time. The bias or “PreSoak” voltage

Figure 12. Simplified model to determine series resistance

should be the same as the sweep start voltage to avoid

24 | WWW.TEK.COM

C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

The corrected capacitance (C

) and corrected

The series resistance (R_S) may be calculated from

ADJ

conductance (G_ADJ) are calculated from the following

the capacitance and conductance values that are

formulas [1]:

measured while biasing the DUT (device under test) in the

accumulation region as follows:

(G² + (2pfC)²)C

__________________

C_ADJ =

aR2 + (2pfC)²

_____

)

_____(2pfC______

R_S =

(G² + (2pfC)²)a_R

___________________

G_ADJ =

______

aR2 + (2pfC)²

[

(

)

]

2pfC

where:

a_R = G - (G² + (2pfC)²)R_S

R_S = series resistance

C_ADJ = series resistance compensated parallel capacitance

G = measured conductance

C = measured parallel capacitance

C = measured parallel capacitance (in strong accumulation)

G_ADJ = series resistance compensated conductance

f = test frequency

G = measured conductance

NOTE: The preceding equations for compensating for series

f = test frequency

resistance require that the CVU be using the parallel model

(Cp-Gp).

R_S = series resistance

For this project, these formulas have been added into the

Formulator so the capacitance and conductance can be

automatically compensated for the series resistance.

WWW.TEK.COM | 25

C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Extracting MOS Device Parameters From C-V Measurements

This section describes the device parameters that are extracted from the C-V data taken in the three test modules in the MOS

Capacitor C-V Project. The parameters are derived in the Formulator and the calculated values appear in the Sheet tab in the

Analyze view of each test as shown in Figure 13.

Figure 13. Extracted C-V parameters shown in the Sheet

Oxide thickness

where:

For a relatively thick oxide (>50Å), extracting the oxide

TOX = oxide thickness (nm)

thickness is fairly simple. The oxide capacitance (C_OX) is the

A = gate area (cm²)

high frequency capacitance when the device is biased for

εOX = permittivity of the oxide material (F/cm)

strong accumulation. In the strong accumulation region,

C_OX = oxide capacitance (F)

the MOS-C acts like a parallel-plate capacitor, and the oxide

thickness (T_OX) may be calculated from C_OX and the gate

10⁷ = units conversion from cm to nm

area using the following equation:

(10⁷)Aε_OX

___________

TOX(nm)⁼

C_OX

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C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Flatband capacitance and flatband voltage

l = extrinsic Debye length, which is calculated as follows:

1/2

Application of a certain gate voltage, the flatband voltage

εSkT

l =

(10^-2)

(

)

(V_FB), results in the disappearance of band bending. At this

q²N

point, known as the flatband condition, the semiconductor

where:

band is said to become flat. Because the band is flat, the

surface potential is zero (with the reference potential being

l = extrinsic Debye length

taken as the bulk potential deep in the semiconductor).

Flatband voltage and its shift are widely used to extract

εS = permittivity of the substrate material (F/cm)

other device parameters, such as oxide charges.

kT = thermal energy at room temperature (293K) (4.046 ×

10^-21J)

V_FB can be identified from the C-V curve. One way is to use

the flatband capacitance method. For this method, the ideal

q = electron charge (1.60219 × 10^-19C)

value of the flatband capacitance (C_FB) is calculated from

the oxide capacitance and the Debye length. The concept

N_X = N at 90% W_MAX or N90W (refer to Nicollian and Brews;

of Debye length is introduced later in this section. Once the

see References) or, when input by the user, N_X = N_A or N_X = N_D

value of C_FB is known, the value of V_FB can be obtained from

10^-2 = units conversion from cm to m

the C-V curve data, by interpolating between the closest

gate-to-substrate (V_GS) values [2].

The extrinsic Debye length is an idea borrowed from plasma

physics. In semiconductors, majority carriers can move

The Debye length parameter (l) must also be calculated

freely. The motion is similar to a plasma. Any electrical

to derive the flatband voltage and capacitance. Based on

interaction has a limited range. The Debye length is used

the doping profile, the l calculation requires one of the

to represent this interaction range. Essentially, the Debye

following doping concentrations: N at 90% of W_MAX (refer

length indicates how far an electrical event can be sensed

to Nicollian and Brews), a user-supplied N_A (bulk doping

within a semiconductor.

concentration for a p-type, acceptor, material), or a user-

supplied N_D (bulk doping concentration for an n-type,

donor, material).

Threshold voltage

The turn-on region for a MOSFET corresponds to the

NOTE: The flatband capacitance method is invalid when

inversion region on its C-V plot. When a MOSFET is turned

the interface trap density (D_IT) becomes very large (10¹²-10¹³

on, the channel formed corresponds to strong generation of

or greater). However, the method should give satisfactory

inversion charges. It is these inversion charges that conduct

results for most users. When dealing with high D_IT values,

current. When a source and drain are added to a MOS-C

consult the appropriate literature for a more suitable

to form a MOSFET, a p-type MOS-C becomes an n-type

method.

MOSFET, also called an n-channel MOSFET. Conversely, an

The flatband capacitance is calculated as follows:

n-type MOS-C becomes a p-channel MOSFET.

C_OX (ε_SA/l) (10²)

___________________

C_FB =

The threshold voltage (V_TH) is the point on the C-V curve

C_OX + (ε_SA/l) (10²)

where the surface potential (φ_S) equals twice the bulk

where:

potential (φ_B). This curve point corresponds to the onset

of strong inversion. For an enhancement-mode MOSFET,

C_FB = flatband capacitance (F)

V_TH corresponds to the point where the device begins to

conduct. The physical meaning of the threshold voltage

C_OX = oxide capacitance (F)

is the same for both a MOS-C C-V curve and a MOSFET

εS = permittivity of the substrate material (F/cm)

I-V curve. However, in practice, the numeric V_TH value for

a MOSFET may be slightly different due to the particular

A = gate area (cm²)

method used to extract the threshold voltage.

10² = units conversion from m to cm

WWW.TEK.COM | 27

C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

The threshold voltage of a MOS capacitor can be calculated

the difference in work necessary to remove an electron

as follows:

from the gate and from the substrate. The work function is

derived as follows:

VTH=VFB^±

4ε_SqN_BULKφ_B

φ_B

E_BG

____

COX

W_MS = W_M - [ WS +_

- φ_B]

where:

V_TH = threshold voltage (V)

W_MS = work function

VFB = flatband potential (V)

W_M = metal work function (V) *

A = gate area (cm²)

W_S = substrate material work function, electron affinity (V) *

C_OX = oxide capacitance (F)

E_BG = substrate material bandgap (V) *

εS = permittivity of the substrate material (F/cm)

φB = bulk potential (V) (Note: The Formulator name for φB is

q = electron charge (1.60219 × 10^-19C)

PHIB)

N_BULK = bulk doping (cm^-3) (Note: The Formulator name for

*The values for W_M, W_S, and E_BG are listed in the Formulator

N_BULK is N90W.)

as constants. The user can change the values depending on

the type of materials.

φB = bulk potential (V) (Note: The Formulator name for φB is

PHIB.)

The following example calculates the work function for

silicon, silicon dioxide, and aluminum:

The bulk potential is calculated as follows:

1.12

____

N_BULK

___

_______

W_MS = 4.1 - [4.15 +_

- φ_B]

(DopeType)

φB = -

(

)

N_i

Therefore,

where:

W_MS = -0.61 + φ_B

φB = bulk potential (V) (Note: The Formulator name for φB is

and

PHIB.)

N_BULK

___

_______

W_MS = -0.61 -

(DopeType)

k = Boltzmann’s constant (1.3807 × 10^-23J/K)

(

)

N_i

T = test temperature (K)

where:

q = electron charge (1.60219 × 10^-19C)

W_MS = work function

N_BULK = Bulk doping (cm^-3) (Note: The Formulator name for

k = Boltzmann’s constant (1.3807 × 10^-23J/K)

N_BULK is called N90W.)

T = test temperature (K)

N_i = Intrinsic carrier concentration (1.45 × 10¹⁰cm^-3)

q = electron charge (1.60219 × 10^-19C)

DopeType = +1 for p-type materials and -1 for n-type

N_BULK = bulk doping (cm^-3)

materials

DopeType = +1 for p-type materials and -1 for n-type

Metal-semiconductor work function

materials

difference

For example, for an MOS capacitor with an aluminum gate

The metal-semiconductor work function difference (W_MS)

and p-type silicon (N_BULK = 10¹⁶cm^-3), W_MS = -0.95V. Also,

is commonly referred to as the work function. It contributes

for the same gate and n-type silicon (N_BULK = 10¹⁶cm^-3),

to the shift in V_FB from the ideal zero value, along with the

W_MS = -0.27V. Because the supply voltages of modern

effective oxide charge [3][4]. The work function represents

CMOS devices are lower than those of earlier devices and

28 | WWW.TEK.COM

C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

because aluminum reacts with silicon dioxide, heavily doped

W_MS = metal-semiconductor work function (V)

polysilicon is often used as the gate material. The goal is

to achieve a minimal work-function difference between

VFB = flatband potential (V)

the gate and the semiconductor, while maintaining the

A = gate area (cm²)

conductive properties of the gate.

For example, assume a 0.01cm², 50pF, p-type MOS-C with a

flatband voltage of -5.95V; its N_BULK of 10¹⁶cm^-3 corresponds

Effective and total bulk oxide charge

can be calculated

to a W_MS of -0.95 V. For this example, Q_EFF

The effective oxide charge (Q_EFF) represents the sum of

to be 2.5 × 10^-8C/cm², which in turn causes the threshold

oxide fixed charge (Q_F), mobile ionic charge (Q_M), and oxide

voltage to shift ~5V in the negative direction. Note that in

trapped charge (Q_OT):

most cases where the bulk charges are positive, there is

a shift toward negative gate voltages. The effective oxide

Q_EFF = Q_F + Q_M + Q_OT

charge concentration (N_EFF) is computed from effective

Q_EFF is distinguished from interface trapped charge (Q_IT), in

oxide charge (Q_EFF) and the electron charge as follows:

that Q_IT varies with gate bias and Q_EFF does not [5] [6]. Simple

Q_EFF

NEFF =______

measurements of oxide charge using C-V measurements

do not distinguish the three components of Q_EFF. These

where:

three components can be distinguished from one another by

temperature cycling [7]. Also, because the charge profile in

N_EFF = effective oxide charge density (cm^-2)

the oxide is not known, the quantity (Q_EFF) should be used as

a relative, not an absolute, measure of charge. It assumes

Q_EFF = effective oxide charge (C)

that the charge is located in a sheet at the silicon-silicon

q = electron charge (1.60219 × 10^-19C)

dioxide interface.

From Nicollian and Brews, Eq. 10.10, we have:

Substrate doping concentration

Q_EFF

VFB - WMS = -_____

The substrate doping concentration (N) is related to the

C_OX

reciprocal of the slope of the 1/C² vs. V_G curve. The doping

where:

concentration is calculated and displayed below the graph

in the moscap-c-2vsv test as follows:

VFB = flatband potential (V)

W_MS = metal-semiconductor work function (V)

NSUB⁼

Δ1/C2

qε_S A²

ΔV_G

Q_EFF = effective oxide charge (C)

where:

C_OX = oxide capacitance (F)

N_SUB = substrate doping concentration

Note that C_OX here is per unit of area. So that:

C_OX(W_MS -V_FB)

q = electron charge (1.60219 × 10^-19C)

_______________

Q_EFF =

A = gate area (cm²)

where:

= permittivity of the substrate material (F/cm)

εS

Q_EFF = effective oxide charge (C)

= gate voltage (V)

C_OX = oxide capacitance (F)

C = measured capacitance (F)

WWW.TEK.COM | 29

C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Doping concentration vs. depth

Summary

(doping profile)

When equipped with the 4210-CVU or 4215-CVU option, the

The doping profile of the device is derived from the C-V

4200A-SCS is a very useful tool for making both C-V and I-V

curve based on the definition of the differential capacitance

measurements on MOS capacitors and deriving many of the

as the differential change in depletion region charges

common MOS parameters. In addition to the MOS Capacitor

produced by a differential change in gate voltage [8].

C-V Project, the 4200A-SCS includes other projects

specifically for testing MOS capacitors. The MOS Capacitor

The standard doping concentration (N) vs. depth (w) analysis

Lifetime Test Project is used for determining generation

discussed here does not compensate for the onset of

velocity and lifetime testing (Zerbst plot) of MOS capacitors.

accumulation, and it is accurate only in depletion. This

The MOS Capacitor Mobile Ion Project determines the mobile

method becomes inaccurate when the depth is less than

charge of a MOS cap using the bias-temperature stress

two Debye lengths. The doping concentration used in the

method. In addition to making C-V measurements, the SMUs

doping profile is calculated as:

can make I-V measurements on MOS caps, including leakage

current and breakdown testing.

-2

1/C

)

qε

References

The moscap-dopingprofile test computes the depletion

E. H. Nicollian and J. R. Brews, MOS Physics and

depth (w) from the high frequency capacitance and oxide

Technology (New York: Wiley, 1982), 224.

capacitance at each measured value of the gate voltage

2. Ibid., 487-488

(V_G) [9]. The Formulator computes each (w) element of the

3. Nicollian and Brews, 462-477.

calculated data array as shown:

4. S.M. Sze, Physics of Semiconductor Devices, 2nd edition.

___

_ -

W = Aε_S (^_

) ⁽¹⁰2⁾

(New York: Wiley, 1985), 395-402.

C C_OX

5. Nicollian and Brews, 424-429.

where:

6. Sze, 390-395.

W = depth (m)

7. Nicollian and Brews, 429 (Figure 10.2).

A = the gate area (cm²)

8. Nicollian and Brews, 380-389.

9. Nicollian and Brews, 386.

C = the measured capacitance (F)

εS = the permittivity of the substrate material (F/cm)

Additional Suggested Reading

C_OX = the oxide capacitance (F)

D.K. Schroder, Semiconductor Material and Device

Characterization, 2nd edition. (New York, Wiley, 1998).

10² = units conversion from cm to m

Once the doping concentration and depletion depth

are derived, a doping profile can be plotted. This is

done in the Graph of the MOS Capacitor Doping Profile

(moscap-dopingprofile) test.

30 | WWW.TEK.COM

Switching Between C-V and

I-V Measurements Using the

4200A-CVIV Multi-Switch and

4200A-SCS Parameter Analyzer

Switching Between C-V and I-V Measurements Using the

4200A-CVIV Multi-Switch and 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Note: Although this application note describes I-V and C-V

Introduction

switching with the 4200A-SCS, beginning with Clarius V1.4

Full parametric characterization of a semiconductor device

or higher, each CVIV channel can be used as a bias tee by

usually requires an array of tests to gather all of the device’s

combining the CVU measurements with the SMU bias.

important parameters. Current-voltage (I-V) tests are used to

With the bias tee capability, C-V measurements can be

determine device parameters like transfer characteristics,

made at ±200 V or 400 V differential.

leakages, and breakdown voltages. Capacitance-voltage

(C-V) tests are used to determine device parameters like

doping concentrations, interface charges, and threshold

4200A-CVIV Operation

voltages. It is very common to perform both I-V and C-V tests

The 4200A-CVIV Multi-Switch is a four-channel multiplexed

on the same device, but the two test types require different

switching accessory for the 4200A-SCS that allows users

test equipment and cabling. These differences make it

to switch seamlessly between I-V and C-V measurements.

difficult to perform I-V and C-V measurements on the same

It accepts four SMUs, one for each channel, and one CVU

device quickly because changing test types typically requires

as inputs. Changing the output mode for each of the

recabling

four channels reconfigures the internal switches of the

the entire system.

4200A-CVIV to route the desired signals to the output

terminals. Figure 2 shows a simplified I-V and C-V switching

When configured with 4200-SMU, 4201-SMU, 4210-SMU, or

diagram of the 4200A-CVIV.

4211-SMU Source Measure Units (SMUs) and the 4210-CVU

or 4215-CVU Capacitance Voltage Unit, the 4200A-SCS

Channel 1 switches

Output 1

Parameter Analyzer is capable of performing both I-V and C-V

SMU1

measurements. However, the SMUs use triaxial cables and

CV HI

the CVU uses SMA coaxial cables. Combining the 4200A-SCS

CV LO

GNDU

Parameter Analyzer with the 4200A-CVIV Multi-Switch

CV GRD

eliminates these difficulties because the 4200A-CVIV is

Channel 2 switches

capable of switching between I-V and C-V measurements

Output 2

SMU2

with no need to change cables or lift probe tips. The

4200A-CVIV is shown in Figure 1. The Clarius software that

runs on the 4200A-SCS makes it simple to control the Multi-

Switch and creates a faster, more efficient device testing

Channel 3 switches

workflow for any application that requires making I-V and C-V

Output 3

SMU3

Channel 4 switches

Output 4

SMU4

Figure 2. A simplified switching diagram for the 4200A-CVIV. All of

the channels are shown in two-wire mode and in the OPEN position.

The 4200A-CVIV has six different output modes for each

Figure 1. 4200A-CVIV Multi-Switch.

channel used for I-V and C-V switching. (There are additional

output modes used for bias tee operation). The I-V and C-V

measurements on the same device.

switching output modes are described as follows:

32 | WWW.TEK.COM

Switching Between C-V and I-V Measurements Using the

4200A-CVIV Multi-Switch and 4200A-SCS Parameter Analyzer

APPLICATION NOTE

• SMU - The SMU signal paths in the 4200A-CVIV are

• GNDU - The ground unit can be switched to any one of

not multiplexed and cannot be switched between

the four output channels. NOTE: Must have 4200A-CVIV

channels. Each SMU channel is directly associated

Hardware Version 2.0 or higher and Clarius V1.4 or

with the channel to which it is connected. For example,

higher.

setting Channel 3 to SMU will pass the signal from the

• OPEN - Configuring any channel to OPEN will open all of

SMU connected to Channel 3 to the output terminals for

the output relays connected to that channel.

Channel 3.

The 4200A-CVIV is controlled using the Clarius software

• CV HI and CV LO - The CVU signal path in the

application that comes with the 4200A-SCS Parameter

4200A-CVIV is fully multiplexed and can be assigned

Analyzer. Switch configurations are controlled by placing

to any of the output channels. CV HI or CV LO can be

the cviv-configure Action from the Action Library into the

assigned to any channel or any combination of channels

project tree.

to perform the desired C-V measurement. For example,

setting Channel 1 to CV HI and Channels 2 and 3 to

The cviv-configure Action is used to switch the channel

CV LO will configure the Multi-Switch to perform a

output configuration, two-wire/four-wire CVU setting,

and the names of the test and channels to be shown on the

C-V measurement on the device connected between

4200A-CVIV display. A cviv-configure Action must be used

Channel 1 and Channels 2/3.

any time the configuration of the 4200A-CVIV needs to

• CV GUARD - This mode of the 4200A-CVIV can be

change. Figure 3 shows an example of the cviv-configure

used to remove undesired capacitances from C-V

Action populated with settings to switch the CVU output

terminals to a MOSFET.

measurements. The CVU guard is the outside shield of

the CVU coaxial cable. For example, setting Channel 4

The cvu-cviv-comp-collect Action performs CVU

to CV GUARD will configure the Multi-Switch to guard

connection compensation through a 4200A-CVIV on

out capacitance from the device terminal connected to

a user-defined configuration. Open, Short, and Load

Channel 4.

correction compensations can be acquired. Connection

Figure 3. The cviv-configure Action options.

WWW.TEK.COM | 33

Switching Between C-V and I-V Measurements Using the

4200A-CVIV Multi-Switch and 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Figure 4. The cvu-cviv-comp-collection Action configured to perform an Open Compensation.

compensation corrects for offset and gain errors caused

by the connections between the CVU and the device

under test. The compensation for each particular switch

configuration is automatically stored so that when a

particular configuration is recalled using the cviv-configure

Action, the compensation will automatically be applied if it

is enabled within a C-V measurement test. Figure 4 shows

the cvu-cviv-comp-collect Action setup to perform an Open

compensation.

Figure 5 shows a screen capture of a project called Diode

Tests that is used to make I-V and C-V measurements

on a diode that is connected to the outputs of Channels

1 and 2. First, compensation is performed using the

cvu-cviv-comp-collect Action. Then the cviv-configure-iv

Action connects SMU1 and SMU2 to Channels 1 and 2 so that

the forward and reverse I-V measurements can be made in

Figure 5. The project tree structure for a diode test that uses the 4200A-CVIV

the two tests that follow. When the cviv-configure-cv Action

to switch between I-V and C-V measurements

is executed, the SMUs are disconnected from the outputs

and the CVU HI and LO terminals are connected to Channels

1 and 2. Finally, a C-V sweep is made on the diode.

34 | WWW.TEK.COM

Switching Between C-V and I-V Measurements Using the

4200A-CVIV Multi-Switch and 4200A-SCS Parameter Analyzer

APPLICATION NOTE

C-V/I-V Switching for Device

Characterization

4200A-CVIV

Both I-V and C-V measurements play a role in the parametric

4-Wire Mode

characterization of semiconductor devices. Two-terminal

Sense

devices require simple I-V sweeps to characterize their DC

Channel 4

OPEN

performance and C-V sweeps to determine the capacitance

Force

between their two terminals at different bias levels. For

Sense

Channel 3

example, full characterization of a diode requires I-V

OPEN

measurements to acquire the forward I-V curve, reverse

Force

leakage curve, and reverse breakdown voltage. C-V

Sense

Channel 2

measurements are used to acquire the diode’s doping

SMU

profile and charge density information.

Force

Sense

Channel 1

Two-terminal Devices

SMU

Force

Two channels of the 4200A-CVIV are used to connect to

the diode for I-V and C-V measurements. Since diodes have

Figure 6. Configuration for I-V characterization of a diode using the

very low impedance forward active characteristics, it’s

4200A-CVIV.

best practice to perform measurements in four-wire mode

to prevent measurement inaccuracies due to losses in

cabling. Four-wire mode, also called remote sense, forces

4200A-CVIV

a test current through one set of cables and measures a

4-Wire Mode

voltage directly at the device under test with another set of

cables. This technique helps remove the effects of cable

Sense

Channel 4

impedance from the measurements.

OPEN

Force

Figure 6 shows the device connections and 4200A-CVIV

Sense

Channel 3

settings for an I-V test on a diode. All of the DC I-V

OPEN

characteristics of the diode are collected in this

Force

configuration. The connections to the diode are made with

Sense

Channel 2

triaxial cables, Model 4200-TRX-.75 (75cm or approximately

If + Iac

CVHI

Force

30 inches). These shielded cables are used to ensure that

both very low current I-V measurements and high frequency

Sense

Channel 1

Vf + V

AC measurements can be made with high accuracy. The

CVLO

Force

device can be a packaged part in a test fixture or located

directly on a wafer in a probe station.

Figure 7. Configuration for C-V characterization of a diode using the

The gray capacitor in Figure 6 (C_d) is the parasitic

4200A-CVIV.

capacitance of the PN junction. The I-V test does not

provide information about this parasitic capacitance. A

Three-terminal Devices

C-V test is necessary to characterize the capacitance of

Three-terminal devices require more complicated I-V

the device. Figure 7 shows the device connections and

characterization and often capacitance measurements

4200A-CVIV settings for a C-V test on a diode. All of the

between multiple combinations of terminals. For example,

connections are identical to the I-V test. When the cviv-

bipolar junction transistors (BJTs) are three-terminal

configure Action is executed in the Clarius software, the

devices that require multiple SMUs to measure their

output is switched from the SMUs to the CVU terminals.

transfer characteristics and produce useful data, such as

Gummel plots. The 4200A-CVIV, when coupled with three

SMUs and one CVU in the 4200A-SCS, can make these

measurements.

WWW.TEK.COM | 35

Switching Between C-V and I-V Measurements Using the

4200A-CVIV Multi-Switch and 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Figure 8 shows the device connections, and 4200A-CVIV

To measure the capacitance between two terminals, it is

settings, for an I-V test on a BJT. The configuration is shown

necessary to guard the third terminal to remove the effects

in two-wire mode, also known as local sense, but remote

of the additional parasitic capacitors. F or example, to

sensing should be used for high current BJTs. All of the

measure the base-emitter capacitance (C_be,), the collector

connections to the BJT are made with the 4200-TRX-.75

is connected to guard. The 4200A-CVIV provides this

triaxial cables. The device can be a packaged part in a test

guard signal with the CV GUARD setting. Figure 10 shows

fixture or located directly on a wafer in a probe station.

the cviv-configure settings that instruct the 4200A-CVIV

to use the CV GUARD signal. In this example, the CV HI

terminal is connected to base (b) through Channel 2, CV LO

4200A-CVIV

is connected to the emitter (e) through Channel 1, and CV

GUARD is connected to the collector (c) through Channel 3.

2-Wire Mode

Sense

Channel 4

OPEN

Force

Sense

Channel 3

I_c

SMU

Force

Sense

Channel 2

I_b

SMU

Force

Vce

Sense

Channel 1

SMU

Force

Figure 8. Configuration for I-V characterization of a BJT using the 4200A-CVIV.

Figure 10. cviv-configure settings for a base-emitter capacitance

measurement on a BJT.

Once the I-V measurements are complete, the 4200A-CVIV

Figure 11 shows the device connections, and 4200A-CVIV

can be seamlessly switched to measure the parasitic

settings, for a guarded capacitance measurement on the

capacitances of the BJT junctions without changing cables

C_be of a BJT.

or removing connections to the device. Figure 9 shows the

parasitic capacitances between the BJT’s terminals to be

measured.

4200A-CVIV

2-Wire Mode

Collector

C_bc

Sense

Channel 4

OPEN

Force

Sense

Base

C_ce

Channel 3

CV GUARD

Guarded

Force

Sense

C_be

Channel 2

Emitter

Iac

CV HI

Force

Figure 9. Parasitic capacitances of a bipolar junction transistor (BJT).

Sense

Channel 1

Vac

C_be

CV LO

Force

Figure 11. Base-emitter capacitance measurement on a BJT

using the 4200A-CVIV.

36 | WWW.TEK.COM

Switching Between C-V and I-V Measurements Using the

4200A-CVIV Multi-Switch and 4200A-SCS Parameter Analyzer

APPLICATION NOTE

The same technique is used to measure the base-collector

Capacitance measurements are often made on MOSFETs

capacitance or the collector-emitter capacitance of the

to explore their basic operation and various parameters.

BJT. The 4200A-CVIV can be controlled by the Clarius

Given that the high frequency operation and switching

software to make all of these measurements automatically

speeds of a MOSFET are dependent on the capacitance of

without moving cables between the terminals. The Clarius

the device, capacitance measurements are often made on

software includes a project (cvu-bjt-cviv) that is configured

various parasitic capacitances of the device, as shown in

to measure these three parasitic capacitances present in

Figure 13. For example, the capacitance between the gate

a BJT using the CVU and the 4200A-CVIV to switch the CVU

and channel (C_gd and C_gs) is important because it creates

between terminals of the device.

the charges necessary for operating the devices. This gate-

channel capacitance depends on the applied voltage and

the operating region.

Four-terminal Devices

Four-terminal devices, such as a MOSFET with a separate

Drain

bulk connection, have more terminal-to-terminal parasitic

C_bd

C_gb

capacitances, and more potential I-V and C-V measurement

combinations than lower terminal count components. The

4200A-CVIV, when fully configured with four SMUs and

Gate

Bulk

one CVU, addresses these measurements with flexible

configurability.

Figure 12 shows the device connections, and 4200A-CVIV

settings, for an I-V test on a four-terminal MOSFET. The

Source

configuration is shown in two-wire mode, also known as

local sense, but remote sensing should be used for high

Figure 13. Parasitic capacitances of a MOSFET.

current MOSFETs. All of the connections to the MOSFET are

made with 4200-TRX-.75 triaxial cables. The device can be a

The C-V characteristics of the capacitor formed between

packaged part in a test fixture or located directly on a wafer

the gate and the source, drain, and bulk of the MOSFET

in a probe station.

structure can be used to determine characteristics of the

MOSFET like the threshold voltage, oxide thickness, oxide

capacitance, and doping density. Figure 14 shows the most

4200A-CVIV

common way of configuring this measurement. The source,

drain, and bulk terminals are physically tied together and

2-Wire Mode

a C-V sweep is performed between the gate and the other

Sense

Channel 4

three terminals.

SMU

Force

Sense

HICUR

Channel 3

HIPOT

SMU

Force

Sense

Channel 2

CVU

SMU

Force

V-ds

LOCUR

Sense

Channel 1

Vgs

LOPOT

SMU

Force

Figure 14. C-V test configuration for a MOSFET.

Figure 12. I-V characterization of a four-terminal MOSFET

using the 4200A-CVIV.

WWW.TEK.COM | 37

Switching Between C-V and I-V Measurements Using the

4200A-CVIV Multi-Switch and 4200A-SCS Parameter Analyzer

APPLICATION NOTE

The CVHI, CVLO, and CV GUARD signals of the 4200A-CVIV

Conclusion

can each be assigned to more than one pin at a time. This

The 4200A-CVIV Multi-Switch makes it easy to perform I-V

removes the need to tie the source, drain, and bulk together

and C-V measurements on the same device without the

physically at the device to perform this measurement;

need to change cables, which could potentially introduce

instead, the connections are made internal to the

errors or damage devices. The 4200A-SCS and Clarius

4200A-CVIV. Figure 15 shows the device connections, and

software make it simple to control the 4200A-CVIV and

4200A-CVIV settings, for this C-V test on a four-terminal

integrate C-V and I-V testing together into a single project

MOSFET. Channels 1, 3, and 4 are all assigned to CVLO in this

that executes seamlessly and continuously.

configuration. Figure 16 shows the equivalent circuit of this

4200A-CVIV configuration.

4200A-CVIV

2-Wire Mode

Sense

Channel 4

CV LO

Force

Sense

Channel 3

CV LO

Force

Sense

Channel 2

Iac

CV HI

Force

Sense

Channel 1

Vdc+Vac

CV LO

Force

Figure 15. C-V characterization of a four-terminal MOSFET using the

4200A-CVIV.

Internally connected

by the 4200A-CVIV

CVHI

4200A-CVIV

CVLO

Figure 16. 4200A-CVIV two-terminal MOSFET C-V test equivalent circuit.

38 | WWW.TEK.COM

Making Femtofarad (1e-15F)

Capacitance Measurements

with the 4215-CVU

Capacitance Voltage Unit

Making Femtofarad (1e-15F) Capacitance Measurements

with the 4215-CVU Capacitance Voltage Unit

APPLICATION NOTE

Introduction

Making Connections to the Device

Typical semiconductor capacitances are in the picofarad

Making the proper connections to the device under test

(pF) or nanofarad (nF) ranges. Many commercially available

(DUT) is crucial for making sensitive low capacitance

LCR or capacitance meters can measure these values using

measurements.

proper measurement techniques including compensation.

For the best results, use only the supplied red SMA cables

However, some applications require very sensitive

for making connections from the CVU to the DUT. The red

capacitance measurements in the femtofarad (fF), or 1e-15,

SMA cables have characteristic impedance of 100 Ω. Two

range. These applications include measuring metal-to-

100 Ω cables in parallel have characteristic impedance of

metal capacitance, interconnect capacitance on a wafer,

50 Ω, which is standard for high frequency sourcing and

MEMS devices such as switches, or capacitance between

measuring applications. The supplied accessories allow

terminals on nano devices. These very small capacitances

connecting to a test fixture or prober with BNC or SMAs

are very difficult to measure without using the proper

connections. Using the supplied torque wrench, tighten the

instrumentation and measurement techniques.

SMA cable connections to ensure good contacts.

Using a tool such as the Keithley 4200A-SCS Parameter

The CVU configured for two-wire sensing is shown in

Analyzer equipped with the optional 4215-CVU Capacitance

Figure 1. The HCUR and HPOT terminals are connected to a

Voltage Unit (CVU) enables the user to measure a wide range

BNC tee to form CVH (HI), and the LCUR and LPOT terminals

of capacitances, including very low values of capacitance,

are connected to form CVL (LO).

<1 pF. The CVU is designed with unique circuitry and is

controlled by the Clarius+ software to support features

and diagnostic tools that ensure the most accurate results.

Using this CVU with proper techniques can enable the user

to achieve very low capacitance measurements with tens of

attofarads (1e-18F) noise levels.

This application note explains how to make femtofarad

capacitance measurements using the 4215-CVU

Capacitance Voltage Unit. This includes making proper

connections and using the proper test settings in the

Clarius software for the best results. Further information on

making capacitance measurements, including cabling and

connections, timing settings, guarding, and compensation,

Figure 1. CVU connections for two-wire sensing.

can be found in the Keithley application note, Making

Optimal Capacitance and AC Impedance Measurements with

An example of four-wire sensing to the DUT is shown in

the 4200A-SCS Parameter Analyzer.

Figure 2. In this case, the HCUR and HPOT terminals are

connected to one end of the device, and the LPOT and LCUR

terminals are connected to the other end of the device.

Four-wire connections to the device facilitate sensitive

measurements by measuring the voltage as close as

possible to the device.

40 | WWW.TEK.COM

Making Femtofarad (1e-15F) Capacitance Measurements

with the 4215-CVU Capacitance Voltage Unit

APPLICATION NOTE

Configuring the Clarius+ Software

for Femtofarad Measurements

Setting up the measurements in the Clarius software

involves selecting the femtofarad project in the Library,

configuring the test settings, and executing the

measurements.

Selecting the femtofarad-capacitance

Project in the Library

A project for making very small capacitance measurements

Figure 2. CVU connections for four-wire sensing.

is included in the Projects Library in the Clarius software.

From the Select view, type in “femtofarad” in the search

For either two- or four-wire sensing, the outside shields

bar. The femtofarad-capacitance project will appear in the

of the coax cables must be connected as close as possible

window as shown in Figure 3. Select Create to open the

to the device to minimize the loop area of the shields. This

project in the project tree.

reduces the inductance and helps to avoid resonance

effects, which can be burdensome at frequencies higher

than 1 MHz.

Keep all cables securely mounted to avoid any movement.

Any movement that occurs in the time between

executing the offset measurements and the actual DUT

measurements can slightly change the loop inductance and

Figure 3. Femtofarad capacitance measurement project in Library.

impact the compensated data.

When measuring very small capacitances, shielding the DUT

Configuring the test settings

becomes important to reduce measurement uncertainties

due to interference. Sources of interference could be AC

Once the project is created, the femtofarad-capacitance

signals or even physical movement. The metal shield should

project appears in the project tree as shown in Figure 4.

enclose the DUT and be connected to the outside shell of

the coax cables.

For low capacitance measurements, it is best to use

four-wire sensing, however, optimal measurements with

two-wire sensing is achievable if the cables are short and

compensation is used.

Figure 4. femtofarad-capacitance project tree.

This project has two tests: 1) the cap-measure-

uncompensated test, which is used to measure the

capacitance of the DUT and, 2) the open-meas test,

which is used to acquire the capacitance of the

cabling and connections. Because of the sensitivity

of these capacitance measurements, the open circuit

measurements are taken with the exact settings used to

measure the DUT. The open circuit measurements are then

WWW.TEK.COM | 41

Making Femtofarad (1e-15F) Capacitance Measurements

with the 4215-CVU Capacitance Voltage Unit

APPLICATION NOTE

subtracted from the capacitance measurements of the

Timing Settings: The timing settings can be adjusted in

DUT. This method enables good measurement results of

the Test Settings window. The Speed mode setting enables

extremely low capacitance.

the user to adjust the measurement window. For very low

capacitance measurements, use the Custom Speed mode to

For successful low capacitance measurements, it is

set the measurement time to achieve the desired accuracy

important to adjust the measure and timing settings

and noise levels. Basically, the longer the measurement

appropriately in the Configure view window. Here are some

time, or window, the less noisy the measurements will be.

suggestions for making optimal adjustments:

The noise is inversely proportional to the square root of the

measurement time as shown in the following equation:

Measure Settings: Some of the settings that the user can

control are the current measure range, AC drive voltage,

and the test frequency. These are important to the

Noise =

√MeasTime

measurement because they are involved in the equation of

The noise can be obtained by calculating the standard

determining the device capacitance. The CVU calculates the

deviation of the capacitance measurements. This

device capacitance from Iac, Vac, and the test frequency

calculation can be done automatically using the Formulator

using the following equation:

in the Clarius software. The cap-meas-uncompensated test

Iac

_________

C =

automatically calculates the noise and returns the value to

2pfVac

the Sheet.

where: C = the device capacitance (F)

The measurement window can be adjusted using the

Iac = AC current measured by the CVU (A rms)

Custom speed mode in the Test Settings window shown in

f = test frequency (Hz)

Figure 5.

Vac = AC drive voltage (V rms)

By observing the relationship in these equations, the

optimal settings for the current measure range, AC drive

voltage, and test frequency can be deduced.

The CVU has three current measurement ranges: 1 µA,

30 µA, and 1 mA. For the lowest capacitance measurements

with the least noise, use the lowest current range, the 1 µA

range.

The level of the AC drive voltage can affect the signal-to-

noise ratio of the measurement. While the AC noise level

stays relatively constant, using a higher AC drive voltage

generates a larger AC current, thus improving the signal-to-

noise ratio. So, it’s best to use an AC drive voltage as high as

possible. In this project, a 1 V AC drive voltage was used.

For very low capacitance measurements, using a test

frequency of about 1 MHz is ideal. With test frequencies

much higher than 1 MHz, transmission line effects increase

Figure 5. Custom Speed mode in Test Settings window.

the difficulty in making successful measurements. At lower

test frequencies, the measurements will lose resolution

The time of the measurement window can be calculated as

since the test frequency and current are proportional.

follows:

Therefore, noisier measurements will result.

Measurement Window = (A/D Aperture Time) * (FilterFactor²

or Filter Count)

42 | WWW.TEK.COM

Making Femtofarad (1e-15F) Capacitance Measurements

with the 4215-CVU Capacitance Voltage Unit

APPLICATION NOTE

Table 1 lists the CVU noise as a function of the measure

Executing the Measurements

window generated with a 1 fF capacitor connected to the

Once the hardware and software are configured, the

terminals of the CVU in a two-wire configuration. The

measurements can be executed. Ideally, the 4200A-SCS

noise was calculated by taking the standard deviation of 15

should be warmed up for at least one hour prior to taking

readings with measurements taken with settings of 0 V DC,

measurements.

1 MHz, and 1 V AC drive voltage. This data verifies that as

the measurement time increases the noise decreases.

Follow these four steps to take compensated

Notice that measurement times of 1 s and above have noise

measurements and repeat the results.

in the attofarad, or 1 E-18F, range. Experimentation may be

required in each test environment to determine the optimal

Measure the Capacitance of the Device. Select the

measurement time for a test.

cap-meas-uncompensated test in the project tree. In

the Configure view, adjust the test settings based on the

Measurement Time (s)

Noise (rms)

device and application. Run the test.

0.001

1.18E-16

2. Measure the Open Circuit. Select the open-meas test in

0.002

9.90E-17

the project tree. Adjust the test settings to be exactly

0.005

9.17E-17

like the test settings in the cap-meas-uncompensated

0.01

7.43E-17

test including the number of data points and voltage

0.02

6.84E-17

steps. Disconnect only the CVH (HCUR and HPOT) cables.

0.05

2.98E-17

Make sure the unterminated cables are capped. Run the

0.1

2.24E-17

open test.

0.2

1.49E-17

3. Analyze the Results. Select the femtofarad-capacitance

0.5

1.15E-17

project in the project tree and select Analyze view.

6.13E-18

A screen capture displaying the compensated 1 fF

5.00E-18

measurements is shown in Figure 6.

3.99E-18

2.77E-18

Table 1. Measurement Time vs Noise of 1 fF capacitor.

Figure 6. Screen capture of the Analyze view Sheet and Graph showing 1 fF measurement.

WWW.TEK.COM | 43

Making Femtofarad (1e-15F) Capacitance Measurements

with the 4215-CVU Capacitance Voltage Unit

APPLICATION NOTE

Notice the most recent capacitance and open

measurements appear in the Sheet along with the noise

calculation. The Data Series from all the tests in the project

tree appear on the right-hand side of the screen. As shown

in Figure 7, the Series List of the Latest Run measurements

from the cap-meas-uncompensated and open-meas

tests are selected. This means that each time the test is

executed, the latest data will be populated in the Sheet.

Figure 8. Test data shown in the Analyze view Sheet.

4. Repeating the measurements. The measurements can

be repeated from the project level by selecting Run. The

compensated readings will automatically be calculated.

However, the open-meas test must be unchecked

as shown in Figure 9. Acquired open measurements

should be repeated periodically if the data appears to

move unexpectedly. This could indicate temperature

variations or cable movements.

Figure 7. Data Series from tests.

A formula has been set up in the Formulator that

automatically calculates the compensated capacitance

measurements by subtracting the open-meas test data

from the cap-meas-uncompensated test data in the

Project level Analyze view Sheet. The graph displays the

compensated capacitance as a function of time. The

CAPACITANCE column in the Sheet lists the compensated

Figure 9. Uncheck the open-meas test to repeat measurements from the

measurements along with the average capacitance of

project level Analyze view.

all the readings. Figure 8 shows the Latest Run Sheet

data with the capacitance measurements (Cp-AB), time,

noise, open measurements, compensated measurements

Conclusion

(CAPACITANCE), and average capacitance (AVG_CAP).

Femtofarad level capacitances can be measured with the

4215-CVU using the Library project, proper connections,

and appropriate measurement techniques and settings.

Using the 4215-CVU with the appropriate measurement

window can enable noise levels in the tens of attofarads

range and below.

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Automating High and Low Frequency

C-V Measurements and Interface

Trap Density (DIT) Calculations of

MOS Capacitors using the 4200A-SCS

Parameter Analyzer

Automating High and Low Frequency C-V Measurements and Interface Trap Density (DIT)

Calculations of MOS Capacitors using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Introduction

The MOS Capacitor

Capacitance-voltage (C-V) measurements are commonly

Figure 1 illustrates the construction of a MOS capacitor.

used in studying gate-oxide quality. These measurements

Essentially, a MOS capacitor is just an oxide placed between

are made on a two-terminal device called a MOS capacitor

a semiconductor and a metal gate. The semiconductor and

(MOS cap), which is basically a MOSFET without a source

metal gate are the two plates of the capacitor. The oxide

and drain. C-V test data on MOS capacitors offers a wealth

functions as the dielectric. The area of the metal gate

of device and process information, including bulk and

defines the area of the capacitor.

interface charges. Many MOS capacitor parameters, such

as oxide thickness, flatband voltage, threshold voltage,

Metal Gate

etc., can be extracted from the high frequency C-V data.

However, one parameter, the interface trap density (DIT),

is typically derived from both the high and low frequency

Metal

C-V measurements. Typically performing both types of

Oxide

C-V sweeps requires two different measuring instruments

Semiconductor

with two different types of cable sets requiring the

user to physically change prober connections between

measurements. However, using the Keithley 4200A-SCS

Parameter Analyzer with the appropriate modules

Back Contact

enables the user to make both high and low frequency

Figure 1. MOS capacitor.

measurements without recabling.

When configured with two source measure units (SMUs)

An important property of the MOS capacitor is that its

with preamps and a capacitance voltage unit (CVU), the

capacitance changes with an applied DC voltage. As a

4200A-SCS Parameter Analyzer can perform both high and

result, the modes of operation of the MOS capacitor change

low frequency C-V measurements. The 4200A-CVIV Multi-

as a function of the applied voltage. Further information

Switch enables the user to automatically switch between

on MOS capacitors and making C-V measurements on

high and low frequency measurements without having to

them can be found in the Keithley application note, “C-V

change cables or lift the probe tips. The Clarius software

Characterization of MOS Capacitors Using the 4200A-SCS

that is included with the 4200A-SCS has an extensive library

Parameter Analyzer”.

with built-in tests for making C-V measurements on MOS

capacitors including a project that combines both high

and low frequency measurements. This project extracts

many common C-V parameters including the interface trap

density (DIT).

This application note discusses how to use the 4200A-SCS

Parameter Analyzer to measure and to automatically switch

between high and low frequency C-V measurements on

MOS capacitors. Basic information on MOS capacitors and

common parameter extractions is also discussed.

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Automating High and Low Frequency C-V Measurements and Interface Trap Density (DIT)

Calculations of MOS Capacitors using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Hardware Requirements for Automating High and Low Frequency C-V

Measurements

To automate between high and low frequency C-V measurements, the 4200A-SCS Parameter Analyzer must be configured

with at least the options listed in Table 1.

Qty

Module

Description

Purpose

4200-SMU, 4201-SMU, 4210-

Source Measure Units (SMU)

Measures very low frequency (VLF) C-V

SMU, or 4211-SMU

Measuring high impedance requires measuring very small

4200-PA

Preamps for SMUs

current

4215-CVU or 4210-CVU

Capacitance Voltage Unit (CVU)

Measures high frequency C-V

Enables automatic switching between low frequency and high

4200A-CVIV

Multi-Switch

frequency measurements

Table 1. Required modules.

Additional cabling is necessary to connect between the output of the 4200A-CVIV and the probe station. We recommend

using the 4200-TRX-.75 Triax Cables on the output of the CVIV. These shielded cables are used to ensure that both very low

current and high frequency AC measurements can be made with high accuracy.

Installing and Configuring the 4200A-CVIV

Installing and configuring the 4200A-CVIV consists of

The output terminals of the CVIV are connected to the

making connections to its input terminals and output

prober. CH1 is connected to the gate of the MOS capacitor

terminals and updating the 4200A-CVIV configuration in the

and is used to measure the capacitance. CH2 is connected

KCON application.

to the substrate, or chuck, and is used to apply the DC

voltage. More information on making proper connections

to make optimal C-V measurements can be found in the

Input and output connections

Keithley application notes listed in Appendix B.

The CVU and the preamps of the SMUs are connected to the

input terminals of the 4200A-CVIV as shown in Figure 2.

Configuring the Setup in KCON

SMU1 and SMU2 are connected to CH1 and CH2. Either two

additional SMUs or channel blocks (included with the CVIV)

After the SMUs and CVU are connected to the CVIV, make

are connected to CH3 and CH4 inputs.

sure the CVIV is connected to the 4200A-SCS with the

supplied USB cable. Close the Clarius application and

open the KCON application on the desktop. At the top of

the screen, select Update. Once the unit is done updating,

SMU4 preamp or

Channel Blocker

select Save. Open Clarius to begin configuring the Clarius

software.

CVU

SMU3 preamp or

Connections

Channel Blocker

SMU2 preamp

SMU1 preamp

Figure 2. Input connections on the 4200A-CVIV.

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Automating High and Low Frequency C-V Measurements and Interface Trap Density (DIT)

Calculations of MOS Capacitors using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Selecting and Configuring the

moscap-cv-dit-cviv Project for

C-V Measurements

The built-in library of the Clarius application includes

several tests and projects that perform high and low

frequency measurements on MOS capacitors. With the

Clarius V1.9 release, a new project, moscap-cv-dit-cviv, has

been added to the Projects Library. This project switches

between high and low frequency C-V sweeps and includes

the calculation of the interface trap density (DIT). This

project can be found in the library in the Select view search

bar by entering DIT. By selecting and then creating the

project, the moscap-cv-dit-cviv project will appear in the

project tree as shown in Figure 3. The following sections will

describe the tests in the project tree.

Figure 3. Project tree of moscap-cv-dit-cviv project.

Acquiring CVU Compensation Data

The first item listed in the project tree is the cvu-cviv-comp-collect Action for acquiring compensation data. CVU Connection

Compensation is used to correct for offset and gain errors caused by the connections between the CVU and the device under

test (DUT). In this case, the connections are from the CVU through CH1 and CH2 of the CVIV and to the cabling to the probe

and chuck. This Action is Run with the probes up. A screen capture of the Configure view of the cvu-cviv-comp-collect Action

is shown in Figure 4.

Figure 4. Configure view of the cvu-cviv-comp-collect Action for acquiring compensation data.

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Automating High and Low Frequency C-V Measurements and Interface Trap Density (DIT)

Calculations of MOS Capacitors using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Switching Between the CVU and SMUs

4200A-CVIV

The cviv-configure-hif-cv and cviv-configure lof-cv actions

2-Wire Mode

are used to automatically switch the outputs of CH1 and

Sense

CH2 of the CVIV between the CVU and the two SMUs. This

Channel 4

CV Guard

prevents unnecessary disturbances of the cabling and

Force

Sense

connections to the device during the test.

Channel 3

CV Guard

Force

The CVU connections through the CVIV are shown in

Sense

Channel 2

Figure 5. In this case, CVH terminal is connected through

CVL (measure)

Gate

Force

CH 1 to the substrate of the MOS cap and forces the DC

Metal

Sense

Channel 1

Oxide

bias voltage. The CVL terminal is connected through CH 2

CVH (force DCV)

Semiconductor

to the gate of the MOS cap and measures the ac current.

Force

DC Vbias = Vsub

Even though CH 3 and CH4 are unused, these channels are

= -Vgate

configured for CV Guard to minimize noise from unwanted

pathways. A screen capture of the cvu-configure-hif-cv

Figure 5. CVU connections through the 4200A-CVIV to the MOS capacitor.

Action is shown in Figure 6.

Figure 6. Configuration view of cviv-configure-hif-cv action.

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Automating High and Low Frequency C-V Measurements and Interface Trap Density (DIT)

Calculations of MOS Capacitors using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Figure 7 shows the SMU connections through the CVIV for

the low frequency C-V measurements. SMU1 is connected

4200A-CVIV

through CH1 to the substrate and SMU2 is connected

2-Wire Mode

through CH2 to the gate. Just like for the high frequency

Sense

Channel 4

CVU measurements, the DC bias is applied to the substrate

SMU4 or Open

Force

so that the gate voltage = (-1)*Vsubstrate.

Sense

Channel 3

SMU3 or Open

Force

Sense

Channel 2

SMU2 - smu_sense

Gate

Force

Metal

Sense

Channel 1

Oxide

SMU1 - smu_src

Semiconductor

Force

dcv_bias = Vsub

= -Vgate

Figure 7. SMU connections through the 4200A-CVIV for MOS capacitor

measurements.

High Frequency Measurements Using the CVU

The 4215-CVU or 4210-CVU Capacitance Voltage Unit can measure capacitance with a range of test frequencies from 1 kHz

to 10 MHz. The moscap-hif-cv test in the project is configured for making a C-V sweep with the CVU. The test parameters,

such as the test frequency, DC bias, and timing settings, can be adjusted in the Configure view of the test, which is

shown in Figure 8. To enable the CVU offset compensation, check the appropriate Compensation boxes in the Terminal

Settings window.

Figure 8. Configure view of the moscap-hif-cv test.

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Automating High and Low Frequency C-V Measurements and Interface Trap Density (DIT)

Calculations of MOS Capacitors using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

This test has calculations in the Formulator for deriving

Low Frequency Measurements

and adjusting for the series resistance. The formulas in this

Using Two SMUs

test are listed in Appendix A. Some of the constants in the

Formulator including the gate area and temperature will

The 4200A-SCS makes low frequency C-V measurements

need to be adjusted prior to executing the test.

using the very low frequency (VLF) C-V technique, which

uses the low current measurement capability of the SMUs

Once the test is Run, the graph is automatically generated.

to perform C-V measurements at specified low frequencies

Figure 9 shows the results of measuring an n-type MOS

in the range of 10 mHz to 10 Hz. The VLF C-V technique

capacitor using the test.

requires two SMUs with preamps.

Keithley application notes for making optimal high

Figure 10 is a simplified diagram of the SMU instrument

frequency C-V measurements on MOS capacitors are listed

configuration used to generate the low frequency

in Appendix B.

impedance measurements. SMU1 outputs the DC bias with

a superimposed AC signal and measures the voltage. SMU2

measures the resulting AC current while sourcing 0 V DC.

More detailed information on the VLF-CV technique can

be found in the Keithley application note, “Performing

Very Low Frequency Capacitance-Voltage Measurements

on High Impedance Devices Using the 4200A-SCS

Parameter Analyzer”.

Capacitor

Test Device

Force HI

SMU1

SMU2

Figure 9. C-V sweep of MOS capacitor using the 4215-CVU.

smu_src

smu_sense

Force LO

(Internally Connected)

SMU1 with preamp:

SMU2 with preamp:

Outputs DCV with

Measures AC current

superimposed ACV and

at 0 V DC.

measures AC voltage.

Figure 10. VLF C-V measurement setup for a MOS capacitor on wafer.

The moscap-lof-cv test in the project tree is used for

making a very low frequency C-V sweep on the MOS

capacitor. Test parameters can be adjusted in the Configure

view, shown in Figure 11.

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Automating High and Low Frequency C-V Measurements and Interface Trap Density (DIT)

Calculations of MOS Capacitors using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Figure 11. Configure view of the moscap-lof-cv test.

Once the test is Run, the graph is automatically generated as shown in Figure 12.

Figure 12. Very low frequency (VLF) C-V sweep of MOS capacitor.

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Automating High and Low Frequency C-V Measurements and Interface Trap Density (DIT)

Calculations of MOS Capacitors using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Executing the moscap-cv-dit-cviv project and parameter extractions

When the moscap-cv-dit-cviv project is selected and is executed from the top of the project tree, the actions and tests will

sequentially execute in their order in the project tree. The high and low frequency C-V measurements are sent to the project

level Analyze Sheet and Graph and are plotted as shown in Figure 13.

Figure 13. HI and LO Frequency C-V curves plotted in the project level Analyze view.

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Automating High and Low Frequency C-V Measurements and Interface Trap Density (DIT)

Calculations of MOS Capacitors using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

The C-V measurements are combined in equations in the formulator to calculate many MOS capacitor parameters including

the flatband capacitance, flatband voltage, oxide capacitance, and the interface trap density as shown in Figure 14.

Appendix A lists all the calculated parameters found at the project level Analyze view as well as in the moscap-hif-cv test in

the project tree.

Figure 14. Project level Formulas List.

Interface Trap Density (DIT)

From the calculated parameters in the project level, the

interface trap density (DIT) is derived and can be plotted.

Interface traps are defects or impurities resulting from

processing or device damage. These traps are located

at the semiconductor interface and can be charged or

discharged and affect the device capacitance. Because

traps may respond slowly to changes in gate voltage, they

affect the device capacitance at high frequencies but not

low frequencies. DIT can be plotted against the interface

trap energy (eV) with respect to mid band gap as shown in

Figure 15.

Figure 15. Interface trap density graphed in project level Analyze View Graph.

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Automating High and Low Frequency C-V Measurements and Interface Trap Density (DIT)

Calculations of MOS Capacitors using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Conclusion

High and low frequency C-V measurements can be automated using two SMUs with preamps, a CVU, the 4200A-CVIV Multi-

Switch, and the Clarius software. From the C-V data, many important device parameters are derived including the interface

trap density. Techniques for making optimal high and low frequency C-V measurements are found in the applications notes

listed in Appendix B.

Appendix A: Project Formulas and Constants

Project Level Calculations in the Formulator

Formula

Description

Adjusted high frequency capacitance from the latest Run of the moscap-hf-cv test:

CHF

CHF= “MOSCAP-HF-CV_LATESTRUN_CADJ”

Since the DC voltage is applied to the substrate, VG=-Vsubstrate, and is updated from the latest Run of the moscap-hf-cv

test: VG= -1*(“MOSCAP-HF-CV_LATESTRUN_DCV_GB”

Low frequency capacitance from the latest Run of the moscap-vlf-cv test:

CLF

CLF=”MOSCAP-VLF-CV_LATESTRUN_MEAS_CP”

Oxide capacitance:

COX

COX = MAX(MAVG(CHAF,2))+1E-15

Interface trap capacitance:

CIT

CIT=(1/(1/CLF-1/COX)-1/(1/CHF-1/COX))

Stretch out factor due to interfacial states:

STRETCHOUT

STRETCHOUT = MAVG((1-CLF/COX)/(1-CHF/COX),5)INVCSQR = 1/(MAVG(CHF,5))^2

Inversed square of high frequency capacitance:

INVCSQR

INVCSQR = 1/(MAVG(CHF,5))^2

Doping density:

NDOPING

NDOPING = ABS(-2*STRETCHOUT/(AREA^2*Q*ES)/(DELTA(INVCSQR)/DELTA(VG)))

Depletion depth (in meters):

DEPTH

DEPTHM = 1E-2*AREA*ES*(1/CHF-1/COX)

Doping density at 90% of maximum depletion depth:

N90W

N90W = AT(NDOPING,FINDLIN(DEPTHM,0.9*MAX(DEPTHM),2))

Debye length (in meters):

DEBYEM

DEBYEM = SQRT(ES*K*TEMP/(ABS(N90W)*Q^2))*1E-2

Flatband capacitance:

CFB

CFB = (COX*ES*AREA/(DEBYEM*1E2))/(COX+(ES*AREA/(DEBYEM*1E2)))

Flatband voltage:

VFB

VFB = AT(VGS,FINDLIN(CHF,CFB,2))

Bulk Potential:

PHIB

PHIB = (-1)*K*TEMP/Q*LN(ABS(N90W)/NI)*DOPETYPE

PSIS-PSIO, which is surface potential:

PSISPSIO

PSISPSIO = SUMMV((1-CLF/COX)*DELTA(VG))*DOPETYPE

Offset in surface potential due to calculation method and flatband voltage:

PSIO

PSIO = AT(PSISPSIO,FINDLIN(VG,VFB,2))

Silicon surface potential, φ_s. More precisely, this value represents band bending and is repeated to surface potential via the

PSIS

bulk potential.

PSIS = PSISPSIO-PSIO

Interface trap energy (eV) with respect to mid band gap:

EIT

EIT = PSIS+PHIB

Interfacial states density (cm^-2eV^-1):

DIT

DIT = CIT/(AREA*Q)

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Automating High and Low Frequency C-V Measurements and Interface Trap Density (DIT)

Calculations of MOS Capacitors using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Constants in Project level Sheet Formulator

Name

Default Value

Unit

Description

1.04E-12

F/cm

Semiconductor permittivity

1 = p-type

DOPETYPE

-1

-1 = n-type

TEMP

300

Test temperature

AREA

0.0025

cm^2

Gate area

1.45E+10

cm^-3

Ni - intrinsic carrier concentration

Formulas for moscap-hf-cv test:

Formula

Description

Gate voltage:

VG = -DCV_GB

Series Resistance calculated from capacitance in strong accumulation and conductance:

RS = (AT(MAVG(GP_GB, 5)/((2*PI*F_GB)*MAVG(CP_GB, 5)), MAXPOS(MAVG(CP_GB, 5))))^2/((1+(AT(MAVG(GP_GB, 5)/((2*PI*F_

GB)*MAVG(CP_GB, 5)), MAXPOS(MAVG(CP_GB, 5))))^2)*(AT(MAVG(GP_GB, 5),MAXPOS(MAVG(CP_GB, 5)))))

Intermediate parameter for calculation of corrected capacitance:

AR = GP_GB-(GP_GB^2 + (2*PI*F_GB*CP_GB)^2)*RS

AR = G - (G2 + (2πfC)2)RS

Corrected capacitance by compensating series resistance:

CADJ

CADJ = ((GP_GB^2) + (2*PI*F_GB*CP_GB)^2)*(CP_GB)/(AR^2 + (2*PI*F_GB*CP_GB)^2)

Oxide capacitance (usually set to max capacitance in accumulation):

COX

COX = MAX(MAVG(CADJ, 2))+1E-15

Appendix B: References

1. Nicollian, E.H. and Brews, J.R. MOS Physics and Technology, Wiley, New York (1982)

2. Schroder, D.K. Semiconductor Material and Device Characterization, 2nd edition (New York, Wiley, 1998)

3. Keithley application notes:

“C-V Characterization of MOS Capacitors Using the 4200A-SCS Parameter Analyzer”.

“Making Optimal Capacitance and AC Impedance Measurements with the 4200A-SCS Parameter Analyzer”.

“Performing Very Low Frequency Capacitance-Voltage Measurements on High Impedance Devices Using the 4200A-SCS

Parameter Analyzer”.

“Switching Between C-V and I-V Measurements Using the 4200A-CVIV Multi-Switch and 4200A-SCS Parameter Analyzer”.

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Making Three-Terminal

Capacitance-Voltage

Measurements Up to 400 V

Using the 4200A-CVIV

Multi-Switch Bias Tee Capability

Making Three-Terminal Capacitance-Voltage Measurements Up to 400 V

Using the 4200A-CVIV Multi-Switch Bias Tee Capability

APPLICATION NOTE

Introduction

The switching speeds of semiconductor devices such as

MOSFETs, IGBTs and BJTs are affected by the capacitance

of the components themselves. In order to design their

circuits for efficiency, designers need to know these

parameters. For example, designing an efficient switch-

mode power supply would require the designer to know the

device capacitance because this would affect the switching

speed and, therefore, the efficiency. This information is

usually provided in a MOSFET’s datasheet.

The capacitance of three-terminal power semiconductor

devices can be looked at in two different ways: at

the component level and at the circuit level. Looking

at the capacitances at the component level involves

Figure 2. Input capacitance for a power MOSFET

characterizing capacitance between every device

terminal. Looking at the capacitance at the circuit level

involves characterizing the combination of component-

level capacitances. For example, Figure 1 illustrates the

component-level capacitances of a power MOSFET.

Figure 1. Component-level capacitances for a power MOSFET

Figure 3. Output capacitance for a power MOSFET

Figures 2 through 4 illustrate the relationship between the

component-level and circuit-level capacitance for a power

MOSFET. Similar capacitance measurements can also be

made for BJT and IGBT devices.

The relationships are derived as follows:

• C_ISS = C_GS + C_GD = input capacitance

• C_OSS = C_DS + C_GS = output capacitance

• C_RSS = C_GD = reverse transfer capacitance

Figure 4. Reverse transfer capacitance for a power MOSFET

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Making Three-Terminal Capacitance-Voltage Measurements Up to 400 V

Using the 4200A-CVIV Multi-Switch Bias Tee Capability

APPLICATION NOTE

Device capacitance typically varies with the applied voltage.

Figure 5 shows the connection of a MOSFET to the CVIV. For

Therefore, complete characterization requires knowledge

this specific application, at least three SMUs and one CVU

of the capacitance at the maximum rated voltage. This

are required to complete the test.

application note explains how the C_ISS, C_OSS and C_RSS

measurements are made using the bias tee capabilities

provided by the 4200A-CVIV Multi-Switch and that were

added in Clarius V1.4. The CVIV can easily switch between

I-V and C-V measurements without recabling. It can also

move the C-V measurements to any device terminal without

recabling or lifting prober needles.

This application note also shows how the instrument DC

output voltage was doubled from 200 V to 400 V for higher

voltage measurements on the drain, which is beneficial for

testing higher power semiconductors, such as GaN devices.

This capability was added in Clarius V1.6 and updated in

Clarius V1.9. This application note assumes the reader is

familiar with making C-V measurements with the Keithley

4200A-SCS using the 4200A-CVIV.

For more information on bias tee capabilities, refer to these

Figure 5. MOSFET connections to the output terminals of the 4200A-CVIV

Keithley application notes:

• Using the 4200A-CVIV Multi-Switch to Make High

Figure 6 shows the actual CVIV connections to a packaged

Voltage and High Current C-V Measurements

MOSFET. Note that all the channels are open on the CVIV.

The four channels of the 4200A-CVIV will be configured

• Switching Between C-V and I-V Measurements Using the

based on the configuration of each test, so no cable

4200A-CVIV Multi-Switch and 4200A-SCS Parameter

reconnections are required for each test.

Analyzer

Device Connections

All the SMU and CVU connections described in this

application note are made through the 4200A-CVIV. The

CVIV could have one 4210-CVU or 4215-CVU and up to four

SMUs connected to a device. Refer to the 4200A-CVIV Multi-

Switch User’s Manual for more information.

Using the 4200A-CVIV offers these advantages:

• User-ready, built-in projects to measure C_ISS, C_RSS and

C_OSS at up to 200 V and 400 V.

• Automated measurements enabled by the 4200A-CVIV

Multi-Switch. There is no need to reconnect the device

or cables.

• Open and short C-V compensation.

Figure 6. Packaged MOSFET connected to the 4200A-CVIV

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Making Three-Terminal Capacitance-Voltage Measurements Up to 400 V

Using the 4200A-CVIV Multi-Switch Bias Tee Capability

APPLICATION NOTE

Configuring the Measurement in Clarius

The library in Clarius has two projects that perform three-terminal capacitance measurements on MOSFETs. Both projects

are similarly configured in Clarius; the difference is with the capability. One project, “MOSFET 3-terminal C-V Test Using

4200A-CVIV Bias Tees,” uses a single SMU on the drain, sweeping from 0 to 200 V. The other project, “MOSFET 3-terminal

C-V tests up to 400 V using 4200A-CVIV Bias Tees,” uses a novel approach to double the voltage to go from 0 to 400 V. This

approach uses three SMUs sweeping simultaneously, one on each terminal, to provide a 400 V DC differential across the

drain.

Figure 7. MOSFET-CVIV-CV-Bias-Tees project using the SweepV user module

Figure 7 shows the “MOSFET 3-terminal C-V Test Using

are called compensation collect actions and are provided in

4200A-CVIV Bias Tees” project that uses the SweepV user

the project tree. Compensation is performed for each test

module in the hivcvulib.

configuration before any test is executed. The 4200A can

store the compensation for each configuration so multiple

This user module enables one sweeping SMU at the drain

tests can be performed.

and capacitance measurements taken at each terminal.

This project has five different configurations: C_GS, C_DS

First, open and short compensations are performed to

C_RSS, C_ISS and C_OSS.

ensure accurate measurements. Specific configuration

steps are necessary to perform these compensations. They

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Making Three-Terminal Capacitance-Voltage Measurements Up to 400 V

Using the 4200A-CVIV Multi-Switch Bias Tee Capability

APPLICATION NOTE

CVIV Configuration

The CVIV must be configured accordingly for each test.

The CVIV has many output modes, which are described in

the user manual. Table 1 lists the various output modes.

Table 1. 4200A-CVIV output modes

4200A-CVIV

Output Mode

Application and Description

Default setting. Also disconnects a channel

Open

from the device.

Used for I-V measurements. Connects Force

SMU

HI and Sense HI to the device.

Used for C-V measurements. Connects the

CV HI

CVU (HPOT and HCUR) to the device.

Figure 8. C_GS configuration

Used for C-V measurements. Connects the

CV LO

CVU (LPOT and LCUR) to the device.

Figure 8 shows the C_GS configuration. This test measures

Used to guard unwanted impedance when

capacitance between the gate and source of the MOSFET

making C-V measurements on multi-

while an SMU sweeps DC voltage at the drain.

CV Guard

terminal devices. Apply CV Guard to the

terminal to be excluded from the C-V

measurement.

Used for I-V measurements. Connects Force

Ground Unit

LO and Sense LO to the device.

Used for C-V measurements. Allows an AC

AC coupled AC ground

path to ground without providing a DC path.

Used for C-V measurements up to 200 V DC

BiasT SMU CV HI and

bias. Allows a DC current of up to 1 A, ideal

BiasT SMU CV LO

for on-state device measurements.

Recommended for C-V measurements

BiasT SMU LO I CV HI

up to 200 V DC bias. Allows a DC current

and BiasT SMU LO I

of up to 100 µA, ideal for off-state device

CV LO

measurements.

Used to guard unwanted impedance when

making C-V measurements on multi-terminal

BiasT SMU AC Gnd

devices. Allows DC bias up to 200 V. Apply

BiasT SMU AC Gnd to the terminal to be

excluded from the C-V measurement.

Figure 9. C_DS configuration

Figure 9 shows the C_DS configuration. This test measures

Figures 8 through 12 indicate states for each channel

capacitance between the drain and source of the MOSFET

of the CVIV for each of the component- and circuit-level

while an SMU sweeps DC voltage at the drain.

capacitance measurements.

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Making Three-Terminal Capacitance-Voltage Measurements Up to 400 V

Using the 4200A-CVIV Multi-Switch Bias Tee Capability

APPLICATION NOTE

Figure 11 shows the C_ISS configuration. This test measures

the input capacitance of the MOSFET while an SMU sweeps

DC voltage at the drain.

Figure 10. C

RSS

and C_GD configuration

Figure 10 shows the C_RSS configuration. This test measures

reverse transfer capacitance of the MOSFET while an SMU

sweeps DC voltage at the drain.

Figure 12. C_OSS configuration

Figure 12 shows the C_OSS configuration. This test measures

the output capacitance of the MOSFET while an SMU

sweeps DC voltage at the drain.

Figure 11. C_ISS configuration

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Making Three-Terminal Capacitance-Voltage Measurements Up to 400 V

Using the 4200A-CVIV Multi-Switch Bias Tee Capability

APPLICATION NOTE

Once the tests are executed, the data is plotted. Figure 13 shows the capacitance characteristics data of a MOSFET as

generated with the 4200A.

Figure 13. Capacitance characteristics of a MOSFET sweep to 200 V

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Making Three-Terminal Capacitance-Voltage Measurements Up to 400 V

Using the 4200A-CVIV Multi-Switch Bias Tee Capability

APPLICATION NOTE

400 V DC Voltage Sweep

A novel method has been developed to take advantage of the 4200A-CVIV Multi-Switch and sweeping multiple SMUs

simultaneously to double the output voltage to 400 V at the MOSFET terminal. These tests are usually done in the OFF state

(V_GS= 0 V). There’s usually one sweeping SMU at the drain and, using the bias tee capabilities built into the 4200A-CVIV, the

capacitance is then measured at each terminal.

Figure 14. Three SMUs sweeping simultaneously

Figure 14 shows three sweeping SMUs connected to the three terminals of the MOSFET. SMU1 and SMU2 will enable a voltage

sweep up to 400 V differential. SMU2 and SMU3 must sweep simultaneously at the same voltage, which enables a 0 V drop at

the gate. Using this method, we can produce a 400 V sweep at the drain.

Note: This method is to be used on packaged devices only, and not for wafer-level devices.

These measurements are performed using the multipleSMU_SweepV user module, available in the hivcvulib user library.

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Making Three-Terminal Capacitance-Voltage Measurements Up to 400 V

Using the 4200A-CVIV Multi-Switch Bias Tee Capability

APPLICATION NOTE

Figure 15. Project for outputting up to 400 V DC differential

Figure 15 shows the MOSFET 3-terminal C-V tests up to 400V using 4200A-CVIV Bias Tees project that uses the user module

multipleSMU_SweepV.

The project tree is set up the same way as the previous project. All of the CVIV configuration actions, including the

compensation, are done in exactly the same way. The only difference is that there are two more SMUs that must be

configured. The device connections are still the same.

By default, the test should sweep from 0 to 400 V on the drain. Both the gate and source SMUs should sweep simultaneously

and at the same voltage. The user is restricted when changes are made to start and stop voltages on the terminals.

The user also has the ability to change the CVU settings such as the frequency, range and speed based on the impedance of

the device being tested.

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Making Three-Terminal Capacitance-Voltage Measurements Up to 400 V

Using the 4200A-CVIV Multi-Switch Bias Tee Capability

APPLICATION NOTE

Figure 16. Capacitance characteristics of a MOSFET sweep to 400 V

Figure 16 shows the C-V sweep up to 400 V on a MOSFET generated by the 4200A-SCS. The differential voltage is a calculated

value. It’s the difference between the drain and the source voltages.

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Making Three-Terminal Capacitance-Voltage Measurements Up to 400 V

Using the 4200A-CVIV Multi-Switch Bias Tee Capability

APPLICATION NOTE

Figure 17. Output data for the 400 V sweep

Figure 17 shows the output data, which lists the sweep voltages on the three terminals. The diffVoltage is the calculated

differential voltage value.

Conclusion

Switching speeds of semiconductor devices like MOSFETs,

Moreover, when measuring capacitance on three-terminal

IGBTs and BJTs are affected by the capacitance of the

devices, one of the terminals is usually not included in the

component itself. This application note demonstrates how

measurement and its capacitance could impact the overall

using the 4200A-CVIV enables making these measurements

measurement. Using a bias tee at every terminal eliminates

at 200 V DC bias without the need to reconnect any cables,

the need for external capacitors or shorts.

which reduces user error and permits automated testing.

We have also shown a new method to double the DC bias of

It also allows measuring circuit-level capacitances directly

the 4200A on three-terminal devices by using three SMUs

without going through component-level capacitances,

sweeping simultaneously. The gate and the source SMUs

which allows the circuit-level designer to get to the desired

sweep at the same polarity simultaneously to avoid an on-

data faster.

state of the device. The drain SMU will sweep the opposite

polarity of the source and gate, so that the differential

voltage is doubled. This supports a voltage sweep up to

400 V at the drain, which is beneficial to test higher power

semiconductors such as GaN.

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Forced Current

Quasistatic C-V Method

for SiC Devices

Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

To avoid problems caused by measuring current and

Introduction

stepping voltages in quasistatic methods, the Keithley

Capacitance voltage (C-V) measurements are used for

4200A-SCS Parameter Analyzer uses the Forced Current

analyzing semiconductor materials and in semiconductor

Quasistatic C-V (Force-I QSCV) technique. This method

device fabrication. C-V is particularly useful for

forces current, measures voltage and time, and derives the

characterizing Metal-Oxide-Semiconductors (MOS). Some

capacitance. Some of the advantages to using the Force-I

of the many MOS device properties extracted from C-V data

QSCV technique on a SiC power MOS device include:

include mobile charges in the oxide, oxide capacitance,

interface traps, doping profile, flat band voltage, doping

• Requires only one SMU with a preamp (other methods

concentration, minority carrier lifetime and input/output

use two).

capacitances.

• Forcing current is faster than force voltage methods.

For most semiconductor C-V measurements, high

• Forcing constant DC current to the DUT allows for a

frequency (typically 100 kHz to 1 MHz) is used. However, for

steady state condition unlike stepping voltages.

some C-V measurements, a low frequency, or quasistatic,

• Measures voltage: avoids instability problems when

technique is required. This is the case for interface trap

using an instrument in low output impedance mode to

density (DIT) measurements on a MOScap, where quasistatic

derive the capacitance.

C-V is able to detect interface traps. For Si MOSFETs, a

• Calculates capacitance from the following equation:

charge pumping technique can be used for determining

DIT. At high frequency, interface traps cannot change state

I = C *

rapidly enough to contribute to the device capacitance. As

a result, both the high and low frequency measurements are

• Performs open correction.

required to determine the number of trapped charges.

• Corrects for leakages.

Available quasistatic C-V solutions usually involve forcing

• Provides similar results to C-V measurements taken

a voltage and measuring current using a source measure

with the Keithley 595 Quasistatic C-V Meter.

unit (SMU). These techniques can be effective on traditional

• Investigating if DIT can be extracted using forward and

silicon MOS devices. However, with SiC MOS devices, the

reverse curves.

higher capacitance makes these ammeter techniques

difficult to use because the higher capacitance can cause

• This technique works on larger capacitances > 20 pF.

unstable results.

Beginning with the Clarius V1.14 Software release, tests that

perform the Force-I QSCV technique are included with the

Clarius Software that comes with the Keithley 4200A-SCS.

These tests are some of many included in the extensive test

library provided in the 4200A-SCS Clarius+ Software Suite.

A single SMU with a preamp is required to run the Force-I

QSCV tests in Clarius.

This application note describes the Force-I QSCV technique,

explains how to use the tests in the Clarius Software,

compares this technique to other methods and derives

calculations for internal charges on a SiC MOSFET from the

forward and reverse C-V sweeps.

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

Force-I QSCV Technique Using

Three Steps

The Force-I QSCV technique uses a single SMU with a

preamp to derive the quasistatic C-V characteristics of

a SiC MOSFET or MOScap. An SMU is an instrument that

sources and measures current and voltage. As shown in

Figure 1, the force HI terminal of the SMU is connected to

the gate of the power MOSFET, and the force LO terminal

of the SMU is connected to the drain and source terminals

shorted together.

Drain

Gate

Power

SMU1

MOSFET

Force I

Measure V, t

Figure 2. Current and voltage timing diagrams for Force-I QSCV test.

Source

Force HI

Step 1. The SMU forces a constant current (+I) and measures

the voltage (V) and time until the voltage reaches a user

defined maximum level, VMax. This step charges the device.

The readings taken during this step are not used for the

Force LO

capacitance measurements.

Step 2. After VMax is reached, the polarity of the current

source changes to -I and the voltage is measured until the

Figure 1. A power MOSFET is connected between the force HI and force LO

predefined VMin is reached. During this step, the reverse

terminals of the SMU.

C-V (Cr) sweep is derived.

The forced current quasistatic C-V method derives forward

Step 3. After VMin is reached, the polarity of the current

and reverse C-V curves using a three-step method by

source changes again to +I and the voltage is measured

forcing positive and negative current while measuring

until VMax is reached. During this step, the forward C-V (Cf)

voltage as a function of time. The constant current provides

sweep is derived.

accurate control of the total charge (Q=∑I*dt) supplied to

the device. Using constant current allows for a steady

Both the forward and reverse C-V curves can be extracted

state condition for the instrument unlike voltage stepping

because both the positive and negative current was forced.

that can cause dynamic changes in the measurement

The derived DUT capacitance (C) is calculated as follows:

equipment. The voltage and current timing diagrams of

the three steps are illustrated in Figure 2 and are further

I = C * (

)^{, therefore C = I ÷}(

)

explained in the paragraphs that follow.

where: I = forced current (A), V = measured voltage (V), t =

time (s), C = derived capacitance (F).

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

Using the Clarius Software for Force-I QSCV

Tests using the Force-I QSCV method are located in both the

The following paragraphs describe the input parameters,

Test and Project Libraries that can be found in the Select

output parameters, and analyzing the results of the Force-I

view by searching for the phrase “force-I QSCV” or just

QSCV test.

“qscv”. Once the tests are found in the Test Library, they can

be selected and then added to the project tree. The Test

Input Parameters

Library includes tests for both a SiC MOSFET (sic-mosfet-

The input parameters for the Force-I QSCV tests appear

force-i-qscv) and a SiC MOScap (sic-moscap-force-i-qscv).

in the Configure View of Clarius as shown in Figure 3. The

These particular tests can be used with other devices, or a

user sets both the maximum and minimum test voltages,

new test can be created by adding a custom test (UTM) to

output current and timing parameters. Open compensation

the project tree and using the force_current_CV user module

and leakage correction are optional and can also be applied

found in the QSCVulib user library.

within the Configure View.

Figure 3. Configure view of the Force-I QSCV test in Clarius.

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

Table 1 lists all the input parameters with their descriptions and comments.

Table 1. Input parameters of Force-I QSCV test.

Input Parameter

Description

Comments

SMU ID

SMU# to be used in the test.

The lower the capacitance, the lower the

Forced Current (A)

DC Current to be applied to DUT.

test current.

The compliance voltage is reached during

Compliance Voltage (V)

Compliance voltage.

the test.

Max Test Voltage (V)

Maximum test voltage to be applied to DUT.

Min Test Voltage (V)

Minimum test voltage to be applied to DUT.

Max Test Time (s)

The maximum allowable test time before the test times out.

Integration time for both voltage and leakage current

PLC

Set from 0.01 to 10

measurements.

Current leakage is measured and corrected

Leakage Correction (A)

Checkbox for leakage correction.

at each point.

Settling time allowed after each voltage step. Setting only

Leakage is accomplished by forcing voltage,

Correction Delay (s)

appears if Leakage Correction enabled.

applying step delay, and measuring current.

Cap Offset

The offset to be applied to each capacitance measurement.

Choose to not enable Open Compensation (None), to

Open Compensation is a two-part process

Open Compensation

measure the offset (Meas Comp), or apply the acquired

that is further explained in the paragraphs

offset (Apply Comp).

below.

The following paragraphs contain further information on

This setting affects the measurement time as well as the

some of the input parameters.

voltage step size, which is the voltage difference between

the readings. Ideally the step size should be between

Forced Current. To choose an appropriate forced current

50 mV and 100 mV. The voltage step size can be calculated

may take some trial and error. The forced current typically

using the DELTA function in the formulator. Increasing the

is in the hundreds of picoamps to nanoamp range for a SiC

PLC will improve noisy readings at the expense of longer

MOSFET. The magnitude of the test current should be about

measurement time.

a third of the magnitude of the maximum capacitance to

be measured. For example, if the maximum capacitance is

Leakage Correction and Correction Delay. By default,

2.4E-9 F than the test current should be about 800E-12 A.

leakage correction is disabled. If it is enabled, current

Using either too low or too high of test current may cause

leakage is measured and corrected at each voltage point.

incorrect results.

Leakage correction is done in three steps:

The C-V forward and reverse sweeps are derived using

Too low of test current may take longer for the device to

constant current.

charge up and the measurement time will be longer. Too

high of a current will cause the test to reach the compliance

2. Then the forward and reverse leakage current is

voltage only after a few measurement points and return an

measured at each voltage point returned in the first

error to the Sheet in the Analyze view.

step.

3. Finally, the measured leakage current is used to

The force current for the open compensation should be in

correct the returned capacitance values (CrCorr and

the picoamp or less range. Too high of a current will cause

CfCorr). The leakage current is measured on a fixed

the SMU to go into voltage compliance with no sufficient

current range and can be plotted in real time. Leakage

number of measurements collected. Too low of a current

correction uses the following equation for corrected

will cause very slow measurements.

capacitance:

PLC. The PLC timing setting adjusts the integration time

C_corrected = C_measured * (1 - I_measured/I_forced)

of the measurement and can be set in the range of 0.01 to

10. However, it’s best to use PLC values between 1 and 6.

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

The corrected reverse capacitance, CrCorr, is plotted against Vr, and the corrected forward capacitance, CfCorr, is plotted

against Vf. If the corrected capacitance appears to be noisy, increase the forced current and repeat the test.

The forced current (displacement current) must be higher than the leakage current otherwise the leakage current cannot be

corrected. The displacement current is defined as I = C*(dV/dt).

An example of QSCV curves with and without leakage correction are shown in Figures 4 and 5. The test was run one time but

both the uncorrected and corrected data were generated. Figure 4 shows the forward (Cf) and reverse (Cr) C-V curves of a

leaky SiC power MOSFET.

Figure 4. Forward and reverse quasistatic C-V curves of a leaky SiC MOSFET.

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

Figure 5 shows the results of the corrected forward (CfCorr) and reverse (CrCorr) C-V curves on the leaky device.

Figure 5. Corrected forward and reverse C-V curves on leaky SiC MOSFET.

Cap Offset and Open Compensation. Both cap offset and

By default, cap offset is set to 0 F, but the user can input

open compensation are used to correct for offsets due

a capacitance value that will be subtracted from both the

to capacitances in the test circuit such as cabling, test

forward and reverse capacitance readings.

fixturing or probes. These two options are displayed in the

Open compensation can be set to None, Measure Comp or

Configure view of the tests as shown in Figure 6.

Apply Comp.

If None is selected, then no open compensation

measurements will be written to a file or applied.

If Measure Comp is enabled, the test is run with an open

circuit with either the device removed from the test fixture

or the probes up. There must be minimum of about 3-5 pF

minimum capacitance to correct, otherwise an error

(-35) will occur meaning that the SMU is in compliance.

Typically, the forced current for an open circuit will be in

the 1 E-13 A or less range to avoid the test from going into

Figure 6. Offset and open compensation window.

voltage compliance. Because the test current is so small,

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

the test will take several minutes to execute and acquire

The Analyze view graph will show the measurements

the offset capacitance. The average of the acquired open

results. The voltage vs. time measurements will appear in

circuit data is stored in a file and will be subtracted from

real time in the left-side graph and the forward and reverse

readings acquired using Apply Comp. The capacitance value

C-V sweeps will appear in the right-side graph after the

that is subtracted is shown in the Sheet as Copen.

voltage measurements are finished.

Once the test is Run with Measure Comp, then the DUT

The data is split into the reverse and forward C-V sweeps to

is connected in the test circuit and the test is Run again

accurately represent the measurements. For the reverse

with Apply Comp enabled. Make sure to adjust the forced

sweep, the reverse voltage (Vr), reverse sweep time (timeR)

current to an appropriate level for the device. When the

and reverse capacitance (Cr) are output. In the forward

test is executed a second time, the average capacitance

sweep, the reverse voltage (Vf), forward sweep time (timeF)

acquired (Copen) from Meas Comp will be subtracted from

and capacitance (Cf) are output.

subsequent readings.

Figure 7 shows the results in the Clarius graph view of

testing a commercially available SiC power MOSFET using

Analyzing the Results

the sic-mosfet-force-i-qscv library test. For this test, a test

Once the test is configured with the proper input settings,

current of 8 e-10 A and 4 PLC were used as test settings.

the test can be executed by selecting Run. When the test

The voltage step size is close to 80 mV using 4 PLC. Notice

is run, a constant current is forced to the DUT as described

in the forward and reverse sweeps there is a shift in the

in Steps 1, 2 and 3 to charge up the device and generate

voltage and peaks in the curves. Peaks were observed on

reverse and forward C-V curves.

the forward sweeps on the right side of the curve and on the

reverse sweep on the left side of the curve. These shifts are

usually attributed to internal device charge movement.

Figure 7. Voltage vs. time (left) and reverse and forward C-V graphs (right) of a SiC MOSFET.

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

Figure 8. Forward and reverse quasistatic C-V sweeps on SiC MOSFET.

Example quasistatic C-V curves from a different

In addition to looking at the data in the Graph tool, several

commercially available SiC MOSFET are shown in Figure 8.

parameters are returned to the Sheet in the Analyze View.

In this case, the forward (red) curve has a “mobile ion” like

These output parameters are listed in the following tables

peak that is not exhibited in the reverse sweep. For this test,

and are separated in the order shown in the Sheet as well as

the input parameters were set as follows: test current 5 e-10

grouped into these categories: primary output parameters,

A, 8 PLC, max voltage 10 V, min voltage -12 V, compliance 20

reverse output parameters, forward output parameters,

parameters used for DIT extraction, and miscellaneous

parameters.

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

Table 2. Primary output parameters.

Output Parameter

Description

Comments

Voltage measured as a function of time across the device. Voltage

Check to make sure the step size is between about

Voltage (V)

= Vg.

50 mV to 100 mV.

Vs (V)

Surface Potential defined as Vs=Vg-(Q/Cox) where Vg=Voltage

charge (C)

Charge is defined as Q=∑I*dt supplied to the device (coulombs)

time (s)

Time at each point

Table 3. Reverse output parameters

Output Parameter

Description

Comments

Vr (V)

Reverse voltage from Step 2.

Vrs (V)

Calculated surface potential for reverse voltage defined in Step 2.

Vsr=Vg-(Q/Cox), where Vg=Voltage

timeR (s)

Time array for the reverse sweep

Cr (F)

Capacitance from reverse voltage sweep

Leakage current is measured by forcing voltage at

Ir (A)

Measured leakage current.

each voltage step in the Cr sweep and then measuring

the current.

CrCorr (F)

Capacitance corrected to compensate for leakage current.

CrCorr = Cox(1-Ir/Iforce) where Iforce = Forced Current

Table 4. Forward output parameters.

Output Parameter

Description

Comments

Vf (V)

Forward voltage from Step 2.

Vfs (V)

Calculated surface potential for forward voltage defined in Step 2.

Vfs=Vg-(Q/Cox), where Vg=Voltage

timeF (s)

Time array for the forward sweep.

Cf(F)

Capacitance from forward voltage sweep.

Leakage current is measured by forcing voltage at

If (A)

Measured leakage current.

each voltage step in the Cf sweep and then measuring

the current after the input Step Delay.

CfCorr (F)

Capacitance corrected to compensate for leakage current

CfCorr = Cox(1-If/Iforce) where Iforce = Forced Current

Table 5. Parameters used for DIT extraction.

Output Parameter

Description

Comments

CrDut (F)

Interpolated reverse capacitance.

CfDut (F)

Interpolated forward capacitance.

CrOnly (F)

Interpolated reverse capacitance with Cox removed.

CfOnly (F)

Interpolated forward capacitance with Cox removed.

An array of values that represent the difference between the

Cdut_diff (F)

Plot with Vdut_diff.

forward (CfOnly) and reverse (CrOnly) DUT capacitance values.

An array of differential voltage values that correspond to the

Vdut_diff (V)

Plot with Cdut_diff.

surface potential

Table 6. Miscellaneous output parameters.

Output Parameter

Description

Comments

Cox (F)

Maximum capacitance of both the Cr and Cf data.

Copen is always returned even though this value

Copen (F)

Value used for open compensation

doesn’t get written to the file unless Meas Comp is

selected.

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

Open Compensation. In most cases of measuring QSCV

Optimizing the Force-I QSCV

on SiC devices, open compensation will not be necessary

Method

because cable and test fixturing capacitance (10 s of pF) is

Minimum Capacitance. The minimum capacitance that

usually much smaller than the DUT capacitance (nF).

can be measured is between 10-20 pF. This method

is recommended for SiC devices that typically have

Force-I QSCV vs. Keithley 595

capacitances in the nF range.

Quasistatic C-V Meter

Electrostatically Shield the Device. Because this method

The Keithley 595 Quasistatic C-V Meter, now obsolete,

involves detecting very small charges, it is important to

was used to make quasistatic C-V measurements on

electrostatically shield the device under test to avoid noisy

semiconductor devices. The 595 used a feedback charge

measurements.

method to measure capacitance. This method measured

Voltage Step Size. The voltage step size should be between

coulombs to derive the capacitance unlike most methods

50-100 mV for optimal results. The voltage step size can be

available today that measure current.

adjusted by changing the PLC. The voltage step size can be

Comparisons were made between forward and reverse C-V

measured using the DELTA function in the Formulator of the

curves taken with the 595 and the Force-I QSCV method on

measured “voltage” in the Sheet.

both SiC MOScaps on a wafer and commercially available SiC

Forced Current. Choosing the appropriate test current may

MOSFETs. Results of the forward and reverse quasistatic

take some trial and error. Too low of current will cause long

C-V curves taken on a SiC MOScap are shown in Figure 9.

test times. Too high of current will cause the test to reach

Notice the curves from the two methods overlap.

compliance.

Figure 9. 595 and Force-I QSCV SiC MOScap forward and reverse quasistatic C-V curves.

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

Figure 10 shows graphs using both methods taken on a packaged SiC MOSFET. Notice the Force-I QSCV curves are less noisy

than the 595 data, but in general, the curves correlate nicely.

Figure 10. Both 595 and Force-I QSCV forward and reverse curves on SiC MOSFET.

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

Force-I QSCV vs. High Frequency C-V

Comparisons of C-V curves taken with the Force-I QSCV method and high frequency AC measurements (using the 4215-CVU

Capacitance Voltage Unit) were also observed. The results are shown in Figure 11. The CVU data (green curve) encompassed

both the forward and reverse quasistatic curves from both the 595 and the Force-I QSCV methods. The high frequency CVU

data did not show any “peaks” in the curve.

Figure 11. High frequency and quasistatic C-V sweeps on packaged SiC MOSFET.

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

C-V Measurements and Interface Trap Density on SiC MOS Devices

At the time of this writing (March 2025), we are in the

These five steps are further explained in the following

process of verifying that the suggested interface trap

paragraphs:

density (DIT) calculations on both SiC MOSFETs and

MOScaps using the Force-I QSCV method correlate

Step 1. Generate Forward and Reverse Quasistatic C-V

with other known techniques, such as the comparison

Curves.

of combined low and high frequency capacitance

Generate forward (Cf) and reverse (Cr) quasistatic

measurements. The following paragraphs discuss these

capacitance vs. gate voltage (Vg) curves on a SiC MOSFET

derivations.

using the Force-I QSCV method.

SiC MOSFETs

From the forward and reverse C-V sweeps there is both

a shift in the voltage between the two curves as well as

Traditionally, the interface trapped charge of a silicon MOS

“peaks” and smaller curve features (see Figures 4 and 5).

cap was extracted from the capacitance difference of a low

We believe both the voltage shift and “peaks” are a result

frequency (quasistatic) C-Vg curve and a high frequency (AC)

of internal devices charges such as trapped charges

C-Vg curve. We’ve learned that to observe internal charges

or mobile ion charge, or charges related to the device

of a SiC MOSFET, the forward and reverse quasistatic C-Vg

structure. Interestingly, when a high frequency C-V sweep is

sweeps can be used to extract this charge.

generated, the voltage shift and peaks are not observed.

Because SiC MOSFETs have significantly more internal

charges than traditional Si devices, the measured

Step 2. Derive Surface Potential (Vs) Arrays for both

capacitance needs to be plotted against the surface

Forward and Reverse Sweeps

potential (Vs) as opposed to the gate voltage (Vg) for

The capacitances of forward and reverse voltage sweeps

calculations of trapped charges. Because charge is

of a MOS device are usually compared at the same gate

measured, the interface potential can be calculated. This

voltage (Vg). Because SiC MOSFETs have significant internal

enables the capacitance to be characterized as a function

charges, we compared the forward and reverse quasistatic

of the interface potential. In standard techniques, it’s

curves as a function of the surface potential (Vs) instead.

difficult to extract the interface potential because it’s

Using Vs corrects for the “shifts” seen in the gate voltage

difficult or impossible to measure the oxide charge at a high

between the forward and reverse curves and allows for

frequency. Therefore, comparisons are usually made as a

the curves to be compared. Accurately measured charge

function of the gate voltage and not the interface potential.

allowed us to correct for the voltage drop across the gate

oxide to extract Vs.

The technique for deriving this interface trap capacitance

can be summarized into five steps:

Figure 12 shows the SMU applying a constant current to a

Generate forward (Cf) and reverse (Cr) quasistatic

SiC MOS DUT as well as the voltages, Vg and Vs. The voltage

capacitance vs. gate voltage (Vg) curves on a SiC

at the gate terminal of the device is Vg. The voltage at

MOSFET using the Force-I QSCV method.

the SiC/SiO2 interface is the surface potential (Vs) and is

2. Derive surface potential (Vs) arrays for both forward

represented by the equation:

and reverse sweeps.

Vs = Vg - Vox, where Vox = Q/Cox

3. Interpolate the forward capacitance (CfDut) and reverse

capacitance (CrDut) at each surface potential point.

4. Subtract the oxide capacitance (Cox) from the forward

(CfDut) and reverse (CrDut) measurements.

5. Calculate the capacitance (CIT) and interface trap

density (DIT) due to trapped charge from the difference

of the forward and reverse curves as a function of the

surface potential.

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

b. Run the linear interpolation twice, once for the reverse

sweep and another for the forward sweep to extract

the interpolated capacitance points. The forward and

reverse interpolated capacitance arrays are CrDut and

CfDut.

Force HI

SiC MOS DUT

Gate

Figure 13 shows both the forward and reverse capacitance

SMU V

Oxide

curves, CfDut and CrDut, plotted as a function of interface

Vs = Vg - Vox

SiC

voltage instead of gate voltage.

Force LO

Figure 12. A SMU connected to SIC MOS Dut with circuit potentials.

First, the reverse and forward capacitance arrays (Cr and

Cf) are analyzed to find the maximum value from either

array. The maximum capacitance is defined as Cox, or oxide

capacitance.

Then, from each gate voltage (Vg), the surface potential

Vs is calculated using the oxide capacitance (Cox) and

calculated charge (Q):

Figure 13. Forward and reverse capacitance curves as a function of Vs.

Vs = Vg -

Cox

Step 4. Subtract the Oxide Capacitance from the Forward

Finally, the surface potential is split into two separate

(CfDut) and Reverse (CrDut) Measurements.

arrays for both sweeps. The output parameter, VsR,

represents the reverse sweep surface potential, and VsF

Subtract and maximum capacitance (Cox) from all CrDut and

represents the forward sweep surface potential.

CfDut values. To do this, the linear interpolation algorithm is

run using the reverse and forward voltage surface potential

Step 3. Interpolate the forward capacitance (CfDut) and

values, VsR and VsF. The forward and reverse interpolated

reverse capacitance (CrDut) at each surface potential

capacitance arrays are calculated, and in each function,

point.

the Cox value is removed at each point, using the following

two equations:

The forward and reverse data sets were collected at

different gate voltages, but they need to be compared at

Cf Only =

the same surface potential. To do this, a linear interpolation

Cf Dut

Cox

algorithm is used.

Cr Only =

The following process is used for linear interpolation:

Cr Dut

Cox

a. Determine the number of voltage step points but using

the following equation:

Vmax - Vmin

∆V =

(points to plot) - 1

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

In Figure 14, with Cox removed, CrOnly and CfOnly are plotted as a function of interface voltage, now in a logarithmic scale.

Figure 14. Cf and Cr curves with Cox removed as a function of Vs.

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

Step 5. Calculate the interface trapped capacitance (CIT) and density (DIT)

Calculate the capacitance (CIT) due to trapped charge from the difference of the corrected forward and reverse curves as a

function of the surface potential.

CIT = [C_Fonly(V_s) - C_Ronly(V_s)] / gate area

The interface trap density (DIT) is also derived using the following equation:

DIT = [C_Fonly(V_s) - C_Ronly(V_s)] / (gate area*q)

Figure 15 shows a plot of the interface trap density (DIT) as a function of surface potential (Vs).

Figure 15. Plotted difference between the interpolated forward and reverse capacitances vs. interface voltage (Vs).

SiC MOScap

For interface trap density (DIT) measurements on a MOScap, a combination of both high and low frequency measurements is

used. When generating both high frequency and quasistatic C-V curves, make sure the voltage step size is much smaller than

the voltage difference between the two curves. The voltage step size can be reduced by decreasing the PLC value.

We are still investigating the DIT extraction of both SiC MOScaps and MOSFETs using the Force-I QSCV technique.

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Forced Current Quasistatic C-V Method for SiC Devices

APPLICATION NOTE

Conclusion

Appendix 1. Error Codes

The Force-I QSCV technique enables

These error codes in Table 7 appear in the first column, first row of the

quasistatic C-V measurements on SiC MOS

Sheet in the Analyze view after the test is executed. Below is a description

devices. This method acquires two sets of

of the error and provide help on what to do.

data from forward and reverse sweeps as well

as voltage vs. time data obtained by forcing

Table 7. Error codes for the force_current_cv user module.

positive and negative currents. With the total

Error

Codes

Description

charge known, this method allows for the

extraction of capacitance and charge at the

OK.

semiconductor interface. Differential analysis

The forced current is less than the minimum current of 5e-14 Amps.

-20

Increase the forced current.

of forward and reverse sweeps enables direct

extraction of the density of interface traps

Min Test Voltage (vLow) or Max Test Voltage (vHigh) exceeds the absolute

-21

voltage limit (vLimit). Decrease the Min or Max Test Voltage or increase the

(DIT).

compliance voltage.

Max Test Voltage (vHigh) is smaller than Min Test Voltage (vLow). Increase

-22

the Max Test Voltage or decrease the Min Test Voltage.

Polarity of the Forced Current (Iforce) is not consistent with polarity of Min

-23

Test Voltage (vLow) and Max Test Voltage (vHigh). Change the polarity of the

forced current.

-30

Selected SMU is not present in the system.

In the initial sweep the absolute measured voltage is greater than the

absolute voltage limit. Increase the compliance voltage. The measured

-35

capacitance is too small to measure. The minimum measurable

capacitance is about 10-20pF.

Internal memory values could not be allocated. Please check system

-37

memory usage.

The initial sweep count is greater than the maximum number of steps.

-40

Increase the forced current, PLC, or maximum number of steps.

Test time during the initial sweep exceeded the maximum time. Increase

-50

the max test time or forced current.

Not enough initial points to continue the test. Decrease the forced current.

-55

Minimum capacitance is too small.

The reverse sweep count exceeded the maximum number of steps.

-60

Increase the forced current, PLC, or maximum number of steps.

Test time during the reverse sweep exceeded the maximum time. Increase

-70

the max test time or forced current.

In the reverse sweep the absolute measured voltage is greater than the

-76

absolute voltage limit. Increase the compliance voltage.

The forward sweep count exceeded the maximum number of steps.

-90

Increase the forced current, PLC, or maximum number of steps.

Test time during the forward sweep exceeded the maximum time. Increase

-100

the max test time or forced current.

In the forward sweep the absolute measured voltage is greater than the

-104

absolute voltage limit. Increase the compliance voltage.

Error during writing the offset to the filesystem. Check write access to C:\\

-110

S4200\\kiuser\\coffset.csv

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Performing Very Low

Frequency Capacitance-

Voltage Measurements on High

Impedance Devices Using the

4200A-SCS Parameter Analyzer

Performing Very Low Frequency Capacitance-Voltage Measurements

on High Impedance Devices Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Introduction

Very Low Frequency C-V Technique

Capacitance measurements on semiconductor devices

Figure 1 is a simplified diagram of the SMU instrument

are usually made using an AC technique with a bridge-

configuration used to generate the low frequency

type instrument. These AC instruments typically make

impedance measurements. This configuration requires a

capacitance and impedance measurements at frequencies

4200A-SCS system with two SMU instruments installed,

ranging from megahertz down to possibly tens of hertz.

with 4200-PA preamps connected to either side of

However, even lower frequency capacitance measurements

the device under test. SMU1 outputs the DC bias with a

are often necessary to derive specific test parameters of

superimposed AC signal and also measures the voltage.

devices such as MOScaps, thin film transistors (TFTs), and

SMU2 measures the resulting AC current while sourcing

MEMS structures. Low frequency C-V measurements are

0 V DC.

also used to characterize the slow trapping and de-trapping

phenomenon in some materials. Instruments capable of

Capacitor

making quasistatic (or almost DC) C-V measurements are

often used for these low frequency impedance applications.

However, the 4200A-SCS Parameter Analyzer uses a

Test Device

Force HI

new narrow-band technique that takes advantage of the

low current measurement capability of its integrated

SMU1

SMU2

source measure unit (SMU) instruments to perform C-V

smu_src

smu_sense

measurements at specified low frequencies in the range

of 10 mHz to 10 Hz. This new method is called the Very Low

Frequency C-V (VLF C-V) Technique.

Force LO

The VLF C-V Technique makes it possible to measure

(Internally Connected)

very small capacitances at a precise low test frequency.

This patent-pending, narrow-band sinusoidal technique

SMU1 with preamp:

SMU2 with preamp:

Outputs DCV with

Measures AC current

allows for low frequency C-V measurements of very high

superimposed ACV and

at 0 V DC.

impedance devices, up to >1E15 ohms. Other AC impedance

measures AC voltage.

instruments are usually limited to impedances up to about

1E6 to 1E9 ohms. The VLF C-V approach also reduces the

Figure 1. Connections for very low frequency C-V measurements.

noise that may occur when making traditional quasistatic

C-V measurements.

Basically, while the voltage is forced, voltage and current

measurements are obtained simultaneously over several

The 4200A-SCS Parameter Analyzer comes with

cycles. The magnitude and phase of the DUT impedance

preconfigured tests and a user library to perform

is extracted from the discrete Fourier transform (DFT)

impedance measurements automatically using this very

of a ratio of the resultant voltage and current sinusoids.

low frequency technique. Because this approach uses the

This narrow-band information can be collected at varying

4200A-SCS’s SMU instruments, no additional hardware or

frequencies (10mHz to 10Hz) to create a complex, multi-

software is necessary if low current I-V characterization

element of the DUT. The resulting output parameters

is already required. This application note describes the

include the impedance (Z), phase angle (θ), capacitance

VLF C-V technique, explains how to make connections

(C), conductance (G), resistance (R), reactance (X), and the

to the DUT, shows how to use the provided software, and

dissipation factor (D).

describes optimizing VLF C-V measurements using the

4200A-SCS.

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Performing Very Low Frequency Capacitance-Voltage Measurements

on High Impedance Devices Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Because the very low frequency method works over a

measures the AC current (SMU2 in Figures 1 and 2). The

limited frequency range, the capacitance of the device

SMU instrument used to measure the AC current should be

under test (DUT) should be in the range of 1pF to 10nF. Table 1

connected to the high impedance terminal of the device

summarizes the VLF C-V specifications (see Appendix A for

(Figure 2).

complete specifications).

MOSCaps on wafer

Table 1. Very Low Frequency C-V specifications.

Measurement

Cp, Gp, F, Z, θ, R, X, Cs, Rs, D, time

Parameters

Frequency Range

10 mHz to 10 Hz

Prober Chuck

Measurement Range

1 pF to 10 nF

Force HI

Typical Resolution

3.5 digits, minimum typical 10 fF

PreAmp

AC Signal

10 mV to 3 V RMS

SMU1

SMU2

±20 V on the High terminal, minus the AC

DC Bias

smu_src

smu_sense

signal, 1 µA maximum

Required Hardware for VLF C-V

Force LO

(Internally Connected)

Measurements

To make very low frequency impedance measurements, the

smr.src is connected

smu_sense is

following hardware is required:

to the chuck. This SMU

connected to the gate

applies the DC and AC

of the MOScap and

voltage and measures

measures the current.

•

4200A-SCS with Clarius software

the voltage.

• Two SMU instruments (4200-SMU, 4201-SMU, 4210-SMU,

or 4211-SMU)

Figure 2. VLF C-V measurement setup for a MOScap on wafer.

• Two 4200-PA Preamps

An example of a MOSCap circuit connected for VLF C-V

• Optional: 4210-CVU or 4215-CVU Capacitance

measurements is shown in Figure 2. Most MOSCaps have

Voltage Unit (CVU) for making high frequency C-V

only a single pad on the top of the wafer, with the backside

measurements

of the wafer used as the common contact for all MOSCaps.

SMU1 outputs the AC+DC voltage and is connected to

Making Connections to the Device

the chuck. The SMU that outputs the voltage is known as

“smu_src” in the software that is included with the system.

To make VLF C-V measurements on a device, connect

The high impedance terminal of the MOSCap is the gate

the DUT between the two Force HI terminals of two SMU

and is connected to SMU2, which is called “smu_sense” in

instruments (4200-SMU, 4201-SMU, 4210-SMU or 4211-SMU)

the software.

with 4200-PA Preamps (Figures 1, 2). The preamp option

is necessary because measuring very high impedances

requires measuring very small currents. With the 4200-PAs,

Using the Clarius Software to

currents of <1E-12A can be measured. Because the VLF

Perform VLF C-V Measurements

C-V method requires measuring small currents, it is best to

use the triax cables that come with the SMU instruments to

The system includes a user library called VLowFreqCV that

make these connections. The method does not support any

contains several user modules that you can use to make low

switching instrumentation between the SMU instrument

frequency C-V measurements. Clarius includes example

preamp and the device under test (DUT). One SMU outputs

tests and projects that are based on these user modules

both the DC and AC voltage (SMU1 in Figures 1 and 2) and

that you can use as templates to develop tests. The example

measures the AC voltage. The other SMU instrument

tests and projects are available in the Library.

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Performing Very Low Frequency Capacitance-Voltage Measurements

on High Impedance Devices Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

You can also build custom tests using these user modules. The VLowFreqCV User Library contains several modules, listed in

Table 2, that can be used in a test in a project. To build a custom test, in the Library, select Custom Test and select the option

“Choose a test from the pre-programmed library (UTM)”. Select Configure. In the right pane, for the User Library, select

VLowFreqCV User Library and then select the appropriate User Module.

Figure 3. Screen capture of vlfcv_measure_dual_sweep_bias_fixed_range user module

Table 2. User Modules in the VLowFreqCV User Library.

Once you’ve added a new module to a project, you need

User Module

Description

to input a few parameters. Many of the parameters are

Measures C, G, Z, theta, R+jX at a fixed

common to all the modules; however, each module has some

vlfcv_measure

DC bias.

unique parameters. Figure 3 illustrates the Key Parameters

Measures C, G, Z, theta, R+jX, time while

view of the vlfcv_measure_dual_sweep_bias_fixed_range

sweeping the DC voltage. Optional dual

vlfcv_measure_dual_

sweep allows sweeping from dcv_bias_start

User Module showing all the user-defined parameters.

sweep_bias

to dcv_bias_stop, with 1 measure point

The adjustable parameters for all the modules are listed in

at dcv_bias_stop, then back down to

Tables 3 through 6.

dcv_bias_start.

Measures C, G, Z, theta, R+jX, time while

The values of the expected capacitance (expected_C) and

sweeping the DC voltage. Measurements

are made on a fixed current range which is

the expected parallel resistance (expected_R) determine

vlfcv_measure_dual_

determined by the expected_C, expected_R

which current range will be used to make the measurement.

sweep_bias_fixed_

and maximum DC voltage. Optional dual

range

sweep allows sweeping from dcv_bias_start

However, choosing specific values is generally not required,

to dcv_bias_stop, with 1 measure point

as setting expected_C = 0 will allow the test routines to

at dcv_bias_stop, then back down to

estimate the C and R to use.

dcv_bias_start.

vlfcv_measure_

Measures C, G, Z, theta, R+jX, time at multiple

The simplest module is vlfcv_measure. It is used in the

sweep_freq

user-specified test frequencies.

Capacitor VLF C-V Measurement (vlf-cap-one-point) test in

vlfcv_measure_

Measures C, G, Z, theta, R+jX, time as a

the Capacitor VLF-CV Project. This test performs a single

sweep_time

function of time.

measurement. The module does not perform any sweeping,

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Performing Very Low Frequency Capacitance-Voltage Measurements

on High Impedance Devices Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

but it allows for all test parameters to be controlled

Table 5. Adjustable parameters in the vlfcv_measure_dual_sweep_freq user

module.

(Table 3). Note that the maximum voltage possible is a

combination of both the AC and DC voltages. The maximum

Parameter

Range

Description

negative DC bias voltage = -20 + (acv_RMS *

). The

SMU instrument to source DC + AC

smu_src

SMUn

voltage waveform and measure AC

maximum positive DC bias voltage = +20 - (acv_RMS *

volts: SMU1, SMU2, SMU3…

Use expected_C = 0 to have the routine auto-detect the

SMU instrument to measure AC

estimated C and R values.

smu_sense

SMUn

current: SMU1, SMU2, SMU3…

Array of Test frequencies in Hertz.

Table 3. Adjustable parameters in vlfcv_measure User Module.

frequency

0.01 to 10

Maximum number of entries limited

to 512, from 0.01 to 10.

Parameter

Range

Description

Estimate of DUT capacitance in

SMU instrument to source DC + AC

expected_C

1e-12 to 1e-8

Farads, use 0 for auto-detect of DUT

smu_src

SMUn

voltage waveform and measure AC

C and R.

volts: SMU1, SMU2, SMU3…

Estimate of resistance parallel to

SMU t instrument o measure AC

expected_R

1e6 to 1e14

smu_sense

SMUn

DUT, in ohms

current: SMU1, SMU2, SMU3…

acv_RMS

30e-3 to 3

AC drive voltage in volts RMS

Test frequency in hertz, from

frequency

0.01 to 10

0.01 to 10.

±20 less

dcv_bias

The DC Voltage applied to the device

(acv_RMS *

)

Estimate of DUT capacitance in

expected_C

1e-12 to 1e-8

Farads, use 0 for auto-detect of DUT

C and R.

Table 6. Adjustable parameters in the vlfcv_measure_sweep_time user module.

Estimate of resistance parallel to

Parameter

Range

Description

expected_R

1e6 to 1e14

DUT, in ohms

SMU instrument to source DC + AC

acv_RMS

30e-3 to 3

AC drive voltage in volts RMS

smu_src

SMUn

voltage waveform and measure AC

volts: SMU1, SMU2, SMU3…

±20 less

dcv_bias

The DC voltage applied to the device

(acv_RMS *

)

SMU instrument to measure AC

smu_sense

SMUn

current: : SMU1, SMU2, SMU3…

Test frequency in Hertz, from 0.01

frequency

0.01 to 10

Table 4. Adjustable parameters in the vlfcv_measure_dual_sweep_bias_fixed_

to 10.

range User Modules.

Estimate of DUT capacitance in

Parameter

Range

Description

expected_C

1e-12 to 1e-8

Farads, use 0 for auto-detect of DUT

C and R.

SMU instrument to source DC + AC

smu_src

SMUn

voltage waveform and measure AC

Estimate of resistance parallel to

expected_R

1e6 to 1e14

volts: SMU1, SMU2, SMU3…

DUT, in ohms

SMU instrument to measure AC

acv_RMS

30e-3 to 3

AC drive voltage in volts RMS

smu_sense

SMUn

current: SMU1, SMU2, SMU3…

±20 less

dcv_bias

The DC Voltage applied to the device

Test frequency in hertz, from 0.01

(acv_RMS *

)

frequency

0.01 to 10

to 10.

Number of points to take as a function

num_points

1 to 512

Estimate of DUT capacitance in

of time

expected_C

1e-12 to 1e-8

Farads, use 0 for auto-detect of DUT

C and R.

Estimate of resistance parallel to

Once any test is executed, several test parameters will be

expected_R

1e6 to 1e14

DUT, in ohms

returned to the Sheet in the Analyze view and can be saved

acv_RMS

30e-3 to 3

AC drive voltage in volts RMS

as an .xls file. These test parameters can also be plotted on

±20 less

the Graph. Table 7 lists the returned test parameters and

dcv_start

Starting DC voltage of the sweep

(acv_RMS *

)

their descriptions. From these returned test parameters,

±20 less

more device extractions can be performed using the

dcv_stop

Stop DC voltage of the sweep

(acv_RMS *

)

mathematical functions in the Formulator. Note that the

±20 less

Step size of the DC voltage. Number

tests return all typical C-V measurement parameters. For

dcv_step

(acv_RMS *

)

of steps limited to 512.

example, both Cp-Gp and Cs-Rs are always returned, even if

Enter 0 for single sweep; enter 1 for

dual_sweep

0 or 1

the test device response only matches the parallel (Cp-Gp).

dual sweep

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Performing Very Low Frequency Capacitance-Voltage Measurements

on High Impedance Devices Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Table 7. Measurements returned for the modules in the VLowFreqCV Library.

MOSFET VLF-CV Project

Returned Test

In the MOSFET VLF-CV Project, there are three tests for

Parameters

Description

the n-fet devices, as shown in Figure 4. Figure 6 shows

Error code from test module execution. Definitions

Status

of the returned errors are listed at the bottom of the

the results of generating a very low frequency dual C-V

Definition tab in the UTM Description.

sweep on an n-MOSFET measured between the Gate

times

Calculated time difference between readings.

terminal and the Drain/Source/Bulk terminals tied together

dcv_bias

Programmed DC voltage applied to the device.

(Figure 5). This C-V sweep was generated using the MOSFET

VLF-CV Sweep (vlf-nmosfet-vsweep-dual) test. Tests

meas_Cp

Measured capacitance in parallel (Cp-Gp).

for measuring capacitance as a function of frequency

meas_Gp

Measured conductance in parallel (Cp-Gp)

(vlf-nmostfet-freq-sweep), as well as a high frequency C-V

meas_freq

Measured test frequency.

test (cvu-nmostfet, taken with the CVU) are also included in

meas_Z

Measured impedance (Z-theta).

the project.

meas_Theta

Measured phase angle in degrees (Z-theta).

meas_R

Real component of the impedance (R + jX).

SMU 1

PreAmp

meas_X

Imaginary component of the impedance (R + jX).

smu_src

SENSE

meas_Cs

Measured AC capacitance in series (Cs-Rs).

Force

FORCE

Triax cable

meas_Rs

Measured resistance in series (Cs-Rs).

SMU 2

PreAmp

DUT

smu_sense

meas_D

Calculated dissipation factor, D.

SENSE

Force

The SMU instrument current range that the

FORCE

meas_irange

Triax cable

measurement was taken.

Figure 5. Connection for MOSFET with the gate connected to SMU2 and, with

the drain-source-bulk tied together and connected to SMU1 (smu_sense).

Using the Example Tests and

Projects in the Library

The Clarius software comes with example tests of very

low frequency C-V measurements on various devices.

Choose Select to search for the examples in either the

Test or Project Libraries. Enter VLF in the search box from

either the Test or Project tab. The Tests or Projects will

automatically be displayed in the Library. Select the desired

Test or Project and add it to the Project tree on the left. Even

though the test and projects were created using specific

devices, these examples can be used on other devices.

Descriptions of the very low frequency C-V projects that can

be found in the Project Library are described in the following

paragraphs.

Figure 6. VLF C-V Sweep of an n-MOSFET measured between the gate to

drain/source/bulk. This graph is from the vlf_nmosfet_vsweep_dual test (user

module vlfcv_measure_dual_sweep_bias_fixed_range).

Figure 4. Project tree of MOSFET VLF-CV project

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Performing Very Low Frequency Capacitance-Voltage Measurements

on High Impedance Devices Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Capacitor VLF-CV Project

Using the VLF C-V method, capacitors can be measured

in the range of 1 pF to 10 nF, and connections are made as

shown in Figure 7. The project has four tests for measuring

capacitors (Figure 8). The Capacitor VLF-CV C-t Sweep (vlf-

cap-time) Test measures the capacitance of a 1pF capacitor

as a function of time (Figure 9). The results of performing a

C-V sweep on a 1 pF capacitor are shown in Figure 10. This

small capacitance was measured at a test frequency of 1 Hz

with capacitance measurement noise levels at less than

±5E-15F. The Formulator can be used to determine the noise

and average capacitance readings easily.

SMU 1

PreAmp

smu_src

SENSE

Force

Figure 9. Results of C-t measurements of nominal 1 pF reference capacitor,

FORCE

Triax cable

using VLF capacitance technique at a test frequency of 1 Hz. This graph is from

SMU 2

the vlf-cap-time test (user module vlfcv_measure_sweep_time).

PreAmp

smu_sense

DUT

SENSE

Force

FORCE

Triax cable

Figure 7. VLF C-V connections for the capacitor. If the test device is on wafer,

see the MOSCap diagram (Figure 2) for connections.

Figure 10. VLF C-V results, at 1 Hz, of a voltage sweep on a 1 pF reference

capacitor. This graph is from the vlf-cap-vsweep test (vlfcv_measure_dual_

sweep_bias_fixed_range user module).

Figure 8. Capacitor tests in the Capacitor VLF-CV Project.

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Performing Very Low Frequency Capacitance-Voltage Measurements

on High Impedance Devices Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

To compare the results of both low and high C-V measure-

ments on one graph, the data can be copied from one

test module into another. Just select and copy the C-V

measurements from the Sheet of one test module and

then paste the data into the columns of the CALC Sheet of

the other test module. The data in the CALC Sheet can be

selected on the graph to plot. To do this, make sure to check

the “Enable Multiple Xs” box in the Graph Definition window.

An example showing both the low and high frequency C-V

measurements on one graph is shown in Figure 12.

Figure 11. A VLF C-V sweep of a MOScap at various frequences from 100mHz to

10Hz created using the MOS Capacitor VLF-CV Project. This graph is from the

vlf-moscap-vsweep-dual test (vlfcv_measure_sweep_bias_fixed_range user

module).

MOS Capacitor VLF-CV Project

The MOScap Project has three tests; all are DC bias sweeps

with two using SMUs for the VLF C-V test DC bias voltage

sweep (vlf-moscap-vsweep-dual and vlf-moscap-vsweep)

and the other using the 4210-CVU or 4215-CVU for higher

frequency testing (cvu-moscap-vsweep). An example of

a MOScap VLF-CV dual sweep generated with various

test frequencies ranging from 0.1 Hz to 10 Hz is shown in

Figure 12. This graph is from the moscap-vsweep-hif-lof test, showing the

Figure 11. This test was performed on a chuck at room

high frequency data from the CVU card along with the VLF C-V data from the

vlf-moscap-vsweep test.

temperature. This sweep is the result of executing the

vlf-moscap-vsweep-dual test in the project. From the low

frequency C-V data, characteristics about the MOScap can

R-C Circuit VLF-CV Project

be determined. The built-in math functions are helpful in

Some devices can be modeled as a parallel RC combination

performing the analysis of these devices from the C-V data.

(connection diagram in Figure 13). The parallel resistance

The connection diagram for the MOSCap is shown in Figure

is usually the leakage resistance of the device. In the

2. The dual sweep functionality aids in determining any

R-C Circuit VLF-CV Project, there are two tests for the

hysteresis behavior in the inversion region of the MOScap

RC device: one is the test for a VLF C-V DC bias sweep

device, where frequency dependence is also observed. Note

(vlf-1nf-1gohm) and the other tests sweeps votage and

that the SMU instrument measuring the low current is not

measures current using an SMU (smu-vsweep). Figure 14

connected to the chuck. Connecting the sensitive (i.e., low-

shows the results of performing a low frequency sweep on

current measurement) instrument to the chuck will result in

a 1.5 nF and 1 GΩ parallel combination. From the bias voltage

noisier measurements.

and the resistance (1/Gp) of the device, the current can be

calculated in the Formulator and displayed on the graph.

In addition to the test that generates VLF C-V

Excessive leakage current can cause erroneous results if

measurements on the MOScap, the project includes a test

the current exceeds the maximum current range for the

to measure high frequency C-V on the MOScap. The high

particular RC combination. To determine the DC leakage

frequency C-V measurements were generated using the

current of an unknown DUT, use the smu-vsweep test, as

CVU, which has a test frequency range of 1 kHz to 10 MHz,

described in the section titled “Testing a Device with VLF

with the example data taken at 100 kHz.

C-V.” More information about making optimal measurements

is described in the next section of this note.

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Performing Very Low Frequency Capacitance-Voltage Measurements

on High Impedance Devices Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Guidance for measurement performance across a range of

SMU 1

D values is shown in Table 8. As the table shows, higher D

PreAmp

smu_src

SENSE

values reduce the accuracy of the reported C measurement.

Force

FORCE

Triax cable

Table 8. VLF C-V typical accuracy vs. D and current measure range for the

SMU 2

PreAmp

sense SMU instrument.

smu_sense

DUT

SENSE

0.01 D

0.1 D

1 D

10 D

Force

FORCE

Triax cable

1 µA

0.6 %

1.6 %

Not Recommended

Figure 13. Connection diagram for parallel RC test device.

100 nA

1.4 %

10 %

Not Recommended

10 nA

0.7 %

4 %

6 %

Not Recommended

1 nA

0.4 %

2 %

2.6 %

3 %

100 pA

0.8 %

0.6 %

2 %

“Not Recommended” means that the typical error is >10%.

For details on specific capacitance and frequency values,

see the VLF C-V Typical Specifications in Appendix A.

If the device is purely capacitive (very low to almost no

leakage current, a D <0.1), then just connect the DUT as

shown in Figure 7 (or Figure 2 if the DUT is on a wafer). After

connection, run the desired test(s). However, if the device

type is new, or its electrical characteristics are unknown,

then use the following procedure. This procedure provides

Figure 14. Results of measuring parallel RC combination of 1.5nF capacitor and

1GΩ resistor. This graph is from the vlf-1nF-1gohm test (vlfcv_measure_dual_

a guideline for determining reasonable parameter values for

sweep_bias_fixed_range user module).

unknown test devices using the parallel (Figure 13). It also

provides guidance for evaluating results.

Testing a Device with VLF C-V

Setup

Dissipation Factor

Connect the DUT as shown in Figure 2. The connection

The parallel resistance of the device under test is a key

must be direct with the supplied triax cables. No

aspect that determines the quality of the capacitance

switching or 4225-RPMs may be in the cable path from

measurement because it causes additional DC current to

the SMU instrument Preamp to the DUT. The VLF C-V

flow, which reduces measurement accuracy. This parallel

method utilizes low current measurements, so ensure

resistance at a given frequency is otherwise expressed as

that appropriate shielding and guarding are used. Use

D, the dissipation factor. Here is the equation for the simple

triax cable and eliminate, if possible, or minimize any

parallel model.

unshielded or unguarded cable runs. For on-wafer

measurements, use triax probe manipulators and

D = Reactance/Resistance = 1/ωRC = 1/2πfRC

guarded probe arms.

2. Open one of the example very low frequencyy tests or

where:

project examples in the Library.

f is the test frequency, in Hz

Initial Screening of DUT characteristics

R is the parallel resistance of the test device, in Ω

3. Choose the SMU instrument IV sweep, smu-vsweep

C is the capacitance of the test device, in farads

test, R-C Circuit VLF-CV Project. Choose voltage start

and stop values for the sweep that match the desired

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Performing Very Low Frequency Capacitance-Voltage Measurements

on High Impedance Devices Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

minimum and maximum DC bias voltages to be used for

Review the plotted data, noting the overall shape and

VLF C-V tests. This test will help determine if the DUT

Y-axis values.

leakage is too high for repeatable, accurate results.

Check the status returned from the test. Status =

4. Run the smu-vsweep test. Review the results on the

0 means that the routine did not detect any errors,

graph or in the Sheet. For best results, the maximum

but the validity of the data must still be assessed;

current should be <±1 µA. If the current >±1 µA, reduce

go to the next step. If there is a non-zero status

the bias voltages until the current <±1 µA. Note these

value, refer to the Table 9 Error Codes to see the

voltages for later testing. These voltages may need to be

explanation and troubleshooting suggestions.

adjusted again as described later in this procedure.

In the Sheet, check the current measurement range

5. Next, choose the vlf-cap-freq-sweep test, Capacitor

used. The column meas_irange, located on the

VLF-CV Project. Enter the desired test frequencies,

right side of the Sheet, shows the current measure

using just five to ten points to span the desired

range used for each point. If this range is 1E-6 (1 µA)

frequency range. If only one test frequency is desired,

or lower, skip to the next step. If any of the measure

use the single point test vlf-cap-one-point instead. Use

range values is 10E-6 (10 µA) or larger, the results for

the default expected_C = 0 and expected_R = 1E+12. Use

these rows are suspect. Change the DC bias voltage

acv_RMS = 0.3V and dcv_bias = 0.0V. This test will help

to reduce the current measure range used for the

determine the dissipation factor D of the DUT.

test. For example, when running a voltage bias

sweep, reduce the start and stop voltage used, for

6. Run the vlf-cap-freq-sweep test. Review the results in

example from ±5 V to ±2 V, and re-run the test. Verify

the Sheet. Review the value(s) in the meas_D column. If

that the new test uses a meas_irange 1E-6 (1 µA) or

|meas_D| <1, then the results are reasonable for the test

lower, then compare the results to the previous run

frequencies and DC bias values that had <±1 µA with the

taken with the 10 µA range. Generally, the results

smu_vsweep test. If |meas_D| <10 then results should

with the 1 µA range are more accurate.

be reasonable for dcv_bias = 0V. If |meas_D| >10, then

this present implementation of VLF C-V may provide

If the Y-axis scale shows the maximum of 7E22 or

unacceptable results or results with fairly large errors

70E21, then an overflow has occurred on one or more

(see Table 8). Note that reasonable values with a low D

measurements in the test. Review the data in the

value at dcv_bias = 0 may provide larger errors as the DC

Sheet, in the meas_Cp column, for entries of 70E21

bias is increased.

or 7E22. There are a few causes of the overflow:

If the overflow values are only at the start and

VLF C-V Characterization of DUT

end of the test, consider reducing the range

7. Configure the desired test, such as the bias sweep

of sweep values to omit the sweep points that

vlf-cap-vsweep (Table 4) or frequency sweep vlf-cap-

cause the overflow values. Another option is

freq-sweep (Table 5) in the Capacitor VLF-CV Project.

to specify appropriate values for expected_C

Use the voltage values determined in the previous step.

and expected R. Before choosing values for

As stated earlier, using expected_C = 0 will perform

expected_C and expected_R, let’s briefly explain

an auto-detect of both the C and R values. For the

how these values affect the test. If the overflow

other parameters, follow the description in the table

values are most or all of the rows in the meas_Cp

corresponding to the test (Tables 3 through 6).

column, it is possible that an incorrect measure

range was used for the test. This means that the

8. Run the test. Because of the Run History feature,

current measure range used for the test was

repeating the test keeps the old data, allowing for

too small for the test parameters and DUT. The

comparison across multiple tests. The test parameters

measure range used for the test is contained

used for each run are in the Settings tab of each Run

in the meas_irange in the Sheet. The current

History. For unknown or new devices, review the

measure range for the sense SMU instrument is

measurements to ensure that the results are reasonable

based on the expected_C and expected_R values.

by evaluating the data in the Sheet as well as the

plotted values.

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Performing Very Low Frequency Capacitance-Voltage Measurements

on High Impedance Devices Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

To change the current measure range for a test,

Try one or more of the following adjustments:

supply an expected_C value that is larger than

a) reduce the DC bias voltage; b) increase

the meas_Cp value. Review the values in the

the acv_RMS = 0.3 V; c) increase the test

meas_Cp column and choose a representative,

frequency.

non-overflow value and use it to calculate the

If the meas_Cp values seem noisy or

expected_C = 2 * chosen meas_Cp value. To

inconsistent, append several tests with

choose a value for expected_R, review the

identical parameter values and review the

meas_Gp column for a representative value. Set

data. If the results are different across

expected_R = 1/(2 * chosen meas_Gp).

each run, this indicates that the system is

e. If one or more of the meas_Cp values is negative:

operating at or near the noise floor, which

means that the capacitance value of the test

Ensure that the DUT connections are good.

device is small, or the test device has a higher

The D may be too high, or the DC current leakage

D value (Table 8).

is too high compared to the capacitance.

If none of these adjustments provides

Review the Sheet for meas_D and meas_

reasonable results, try a higher frequency C-V

irange values. If D > ~10 and or meas_irange is

test using the CVU, if available.

≥10 nA, the results may have a larger error.

9. Add tests, such as the capacitance vs. time (test vlf-

Consult Table 8. Compare the current

cap-time) or more DC bias sweeps at additional test

measure range (in the meas_irange) column

frequencies. Recall that data may be saved in .xls or

to the corresponding row in Table 8. Note that

.csv file formats by using the Save Data button in the

the higher D values are more difficult to test.

Analyze pane.

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Performing Very Low Frequency Capacitance-Voltage Measurements

on High Impedance Devices Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Table 9. VLF C-V error codes and descriptions.

Error

Code

Description

Explanation and Troubleshooting Recommendation

Test executed with no errors

No software or operational errors were detected.

Specified SMU instrument is not available in the chassis. For example, if SMU5 is entered, but there are

-16001

smu_src is out of range

only four SMU instruments in the 4200 chassis, then this error will occur. Modify SMU instrument string

to an available SMU instrument number: SMU1, SMU2, SMU3 …

Specified SMU instrument is not available in the chassis. For example, if SMU5 is entered, but there are

-16002

smu_sense is out of range

only four SMU instruments in the 4200 chassis, then this error will occur. Modify SMU instrument string

to an available SMU number: SMU1, SMU2, SMU3 …

-16003

Frequency is out of range.

Ensure that the test frequency is within the range of 10mHz to 10Hz, inclusive

-16004

acv_RMS is out of range

Make sure that the RMS voltage is within the range of 0.01V to 3.0V, inclusive

Modify the DC or AC voltage bias to ensure that the ±20V maximum is not exceeded. Maximum negative

-16005

dcv_bias is out of range

voltage = -20 + (AC voltage * )

Maximum positive bias voltage = 20 - (AC voltage * √_2)

-16006

hold_time is out of range

This error is unused for the VLowFreqCV routines.

-16007

delay_time is out of range

This error is unused for the VLowFreqCV routines.

-16008

Too few points per period

This error indicates that the test was aborted by the operator.

Output array sizes are not

-16009

Make sure all output array sizes are the same value and are not greater than 4096.

equal, or are larger than 4096.

Current measurement over-range occurred and returned values are set to 7E22 (70E21).

Over range indication

Troubleshooting:

-16010

detected.

Review the value in the meas_CP column of the Sheet, looking for the overflow values (7E22 or 70E21).

Follow the process given in Step 8d.

Results array size is less than

-16011

the number of points in the

Increase the size of all output arrays to be equal to the number of points in the sweep.

sweep.

Cannot estimate expected_C or expected_R. This error occurs only when expected_C = 0. Input a

Could not collect enough data

-16012

estimated non-zero value for expected_C. Review the meas_Cp values in the Sheet for non-overflow

to perform measurement.

values. Set estimated_C = 2 * non-overflow meas_Cp

-16013

Unable to allocate memory.

This error is unused for the VLowFreqCV routines.

-16014

Current range is out of range.

This error is unused for the VLowFreqCV routines.

Irange_sense and expected_C

-16015

This error is unused for the VLowFreqCV routines.

cannot be 0 at the same time

-16016

expected_C is out of range

expected_C must be 0 (auto-detect C) or between 1E-15 and 1E-3, inclusive.

This test requires preamp is

Make sure preamp is connected to each SMU used in the test. If reconnecting preamps, run run KCON

-16017

connected to smu_sense

and choose “Update PreAmp and RPM Configuration” in the Tools menu.

Invalid start, stop, step DC

Correct the values for the voltage bias sweep. dcv_bias_step cannot be 0, unless dcv_bias_start =

-16018

bias sweep values.

dcv_bias_stop. If dcv_bias_start = dcv_bias_stop, then dcv_bias_step must = 0.

Output array sizes are less

-16019

than number of points in

Increase the size of all output arrays to be equal to the number of points in the sweep.

sweep.

Invalid combination of start,

Correct the values for the voltage bias sweep. dcv_bias_step cannot be 0, unless dcv_bias_start =

-16020

stop, step dc bias sweep

dcv_bias_stop. If dcv_bias_start = dcv_bias_stop, then dcv_bias_step must = 0.

values.

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Performing Very Low Frequency Capacitance-Voltage Measurements

on High Impedance Devices Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Guidelines for Making Optimal

Choosing the Correct “expected_C” and

“expected_R” Values

Measurements and Troubleshooting

In most cases, expected_C should be 0 and the expected_R

Techniques

= 1E12 (both are the default values). When expected_C = 0,

When making high impedance, very low frequency C-V

the VLF C-V routine will determine estimated values for

measurements using the SMU instruments, various

both C and R of the device under test. The estimated R and C

techniques must be used to optimize measurement

values determine the SMU instrument measurement range.

accuracy. These techniques include implementing

If these values are chosen incorrectly, measurement errors

low current measurement practices and choosing the

or measurement range overflow may result (see Table 9,

appropriate settings in the software.

error code -16010 for more information). However, in some

cases, entering a non-zero estimated capacitance for

Implementing Low Current Measurement

expected_C may provide better results for higher D devices

Techniques

or larger DC bias tests. To calculate a value of expected_C,

multiply a non-overflow value from the meas_Cp column by

Because using the very low frequency impedance

two and enter this value into the test definition expected_C.

measurement method involves measuring picoamp to

femtoamp current levels, low current measurement

To determine if a device is compatible with the present

techniques must be implemented. Use the triax cables

VLF C-V approach, measure the DC resistance of the DUT,

that come with the 4200A-SCS, which are shielded and

performing an I-V test using the smu-vsweep test, R-C

will allow making a guarded measurement, if necessary.

Circuit VLF-CV Project. Use the same test voltages in the I-V

To reduce the noise due to electrostatic interference,

sweep that will be used in the impedance measurements.

make sure the device is shielded by placing it in a metal

Additionally, performing a single measurement (test vlf-cap-

enclosure with the shield connected to the Force LO

one-point) or frequency sweep (test vlf-cap-freq-sweep) at

terminal of the 4200A-SCS. Detailed information on low

a DC bias of 0 V will determine the D of the device. Refer to

current measurement techniques can be found in Keithley’s

“Testing a Device with VLF C-V” and Table 8 for additional

Low Level Measurements Handbook. Also, ensure that the

information.

triax cable is directly connected to the DUT or probe pins;

do not use any switching matrix or 4225-RPM in the SMU

Conclusion

instrument signal path.

The 4200A-SCS contains a tool for performing very low

frequency C-V measurements using the SMU instruments

and preamps. This method enables the user to perform low

capacitance measurements at a precise test frequency in

the range of 10 mHz to 10 Hz. The Clarius software included

with the system enables the user to execute these low

impedance measurements easily and extract important

parameters about the DUT. When combined with the 4210-

CVU or 4215-CVU Capacitance Voltage Unit, the 4200A-SCS

offers the user a single system that can perform both high

and low frequency measurements.

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Performing Very Low Frequency Capacitance-Voltage Measurements

on High Impedance Devices Using the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

TYPICAL MEASUREMENT ACCURACY²

Appendix A

Measured

C Accuracy @

Frequency

Capacitance

300 mV rms¹

30 mV rms¹

Very Low Frequency C-V Typical

1 pF

10%

13%

Specifications

10 pF

10%

MEASUREMENT FUNCTIONS

10 Hz

100 pF

Measurement Parameters: Cp+Gp, Cp+D, Cs, Rs+Cs, R+jX, Z,

1 nF

theta, frequency, voltage, time.

10 nF

Connector Type: Two triax (female) connectors.

1 pF

10 pF

TEST SIGNAL

Frequency Range: 10 mHz to 10 Hz.

1 Hz

100 pF

Minimum Resolution: 10 mHz

1 nF

Signal Output Level Range: 10 mV rms to 3 V rms.

10 nF

1 pF

DC BIAS FUNCTION

10 pF

DC Voltage Bias:

100 mHz

100 pF

Range: ±20 V¹.

1 nF

Resolution: 0.5 mV.

10 nF

Accuracy: ±(0.02% + 1.5 mV).

Maximum DC Current: 1 µA.

1 pF

10%

10 pF

SWEEP CHARACTERISTICS

10 mHz

100 pF

Available Test Types: Linear bias voltage sweep (up or down),

1 nF

frequency list sweep, sample (time), single point

10 nF

Maximum Number of Measurement Points: 512.

INCLUDED LIBRARIES

NOTES

• C-V, C-t and C-f modules

±20 V maximum includes the DC Bias and the AC Test

• Includes test and projects for:

Signal peak voltage. Maximum negative bias voltage =

-Capacitor

-20 + (AC voltage *

). Maximum positive bias voltage =

-MOSCAP

20 - (AC voltage *

-nMOS FET

2. Test device must have dissipation factor D_X <0.1. All data

-R-C circuit

shown for DC Bias voltage = 0 V.

REQUIRED HARDWARE and SOFTWARE

All specifications apply at 23°C ±5°C, within one year of

•

4200A-SCS

calibration, RH between 5% and 60%, after 30 minutes of

warmup.

• Two SMU instruments, 4200-SMU, 4201-SMU, 4210-SMU or

4211-SMU, with Pre-amplifiers (4200-PA)

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Electrical Characterization of

Carbon Nanotube Transistors

(CNT FETs) with the 4200A-SCS

Parameter Analyzer

Electrical Characterization of Carbon Nanotube Transistors

(CNT FETs) with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Introduction

The Carbon Nanotube Transistor

Carbon nanotubes (CNTs) have been the subject of a lot of

A single semiconducting CNT can be used as the conducting

scientific research in recent years, due not only to their

channel between the source and drain of a FET. Figure 1

small size but to their remarkable electronic and mechanical

illustrates a back-gated Schottky barrier CNT FET. Two

properties and many potential applications. The problems

metal contacts are located across both ends of the CNT

associated with attempting to scale down traditional

to form the Source and Drain terminals of the FET. The

semiconductor devices have led researchers to look into

CNT is placed atop an oxide that sits above a doped silicon

CNT-based devices, such as carbon nanotube field effect

substrate, which forms the Gate terminal. Connections are

transistors (CNT FETs), as alternatives. Because they are

made to the three DUT terminals to perform the electrical

not subject to the same scaling problems as traditional

measurements.

semiconductor devices, CNT FETs are being studied for

a wide variety of applications, including logic devices,

CNT

memory devices, sensors, etc. The research on these

Source

Drain

devices typically involves determining various electrical

parameters, which may include current-voltage (I-V), pulsed

SiO2

I-V, and capacitance (C) measurements. Characterizing the

Si Gate

electrical properties of delicate nanoelectronic devices

requires instruments and measurement techniques

optimized for low power levels and high measurement

Figure 1. Back-gated carbon nanotube transistor

sensitivity.

The 4200A-SCS Parameter Analyzer offers a variety of

Making Electrical Measurements

advantages for electrical characterization of CNT FETs.

with the 4200A-SCS

This configurable test system can simplify these sensitive

The 4200A-SCS is supplied with a test project for making

electrical measurements because it combines multiple

some of the most commonly used electrical measurements

measurement instruments into one integrated system

for CNT FETs. This project, the Carbon Nanotube Transistor

that includes hardware, interactive software, graphics,

Characterization Project (cntfet), includes tests for I-V,

and analysis capabilities. The system comes with pre-

pulsed I-V, and C-V measurements. The I-V tests are

configured tests for performing electrical measurements

performed using two Source Measure Units (SMUs), 4200-

that have been optimized to ensure accurate results on

SMU, 4201-SMU, 4210-SMU, or 4211-SMU, both with the

CNT FETs. This application note explains how to optimize

4200-PA Preamp option. The pulsed and transient I-V

DC, pulsed I-V, and C-V measurements on a CNT FET using

measurements are made using the 4225-PMU Ultra-Fast

the 4200A-SCS Parameter Analyzer. It includes detailed

I-V Module (PMU) with two 4225-RPM Remote/Preamplifier

information on proper cabling and connections, guarding,

Switch options. Finally, the C-V measurements are

shielding, noise reduction techniques, and other important

performed using the either the 4210-CVU or 4215-CVU C-V

measurement considerations when testing carbon

Measurement Module (CVU).

nanotube transistors.

The cntfet project is included with all 4200A-SCS

systems. Figure 2 shows the cntfet project running in the

Clarius application.

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Electrical Characterization of Carbon Nanotube Transistors

(CNT FETs) with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Figure 2. The cntfet project for the 4200A-SCS

Current-Voltage Measurements

The I-V characteristics of a CNT transistor can be used to

voltage; they have picoamp sensitivity and can be current-

extract many of the device’s parameters, study the effects

limited to prevent damage to the device. In this diagram,

of fabrication technique and process variations, determine

SMU1 is connected to the Gate of the CNT FET and SMU2 is

the quality of the contacts, etc. Figure 3 illustrates a DC I-V

connected to the Drain. The Source terminal is connected to

test configuration that incorporates two SMUs. These SMUs

the Ground Unit (GNDU) or to a third SMU if it is necessary to

are capable of sourcing and measuring both current and

source and measure from all three terminals of the FET.

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Electrical Characterization of Carbon Nanotube Transistors

(CNT FETs) with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

CNT

Source

Drain

SiO2

Si Gate

Ground Unit

SMU1

SMU2

or SMU3

Steps V

Sweeps V

(if required)

Measures I

Figure 3. Circuit diagram for measuring the DC I-V characteristics of a CNT FET

In this example, the 4200A-SCS’s Clarius software is set up to measure a DC drain family of curves (V_ds-Id). As SMU1 steps

the gate voltage (V_g), SMU2 sweeps the drain voltage (V_d) and measures the resulting drain current (I_d). Figure 4 shows the

resulting FET characteristics generated using the CNT FET project.

Figure 4. DC I-V drain family of curves measured by the 4200-SMU Source Measure Unit

Without changing connections to the device, 4200A-SCS’s interactive Clarius software simplifies performing other common

I-V tests such as the drain current (I_d) vs. gate voltage (V_g) curves. For this test, the gate voltage is swept and the resulting

drain current is measured at a constant drain voltage. The results of an I_d-V_g curve at a constant drain voltage are shown in

Figure 5. The drain voltage can also be stepped as the gate voltage is swept.

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Electrical Characterization of Carbon Nanotube Transistors

(CNT FETs) with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Figure 5. Drain current vs. gate voltage of CNT FET.

Optimizing DC measurements

The following techniques will improve the quality of DC

• Use Proper Speed Modes: The Test Settings pane also

measurements made on CNT FETs with the 4200A-SCS:

offers Speed Modes, including Delay and Filter Factor

settings, which affect the settling time of the reading,

• Limit Current: To prevent damage to the device while

as well as the integration time of the measurement.

performing I-V characterization, the user should limit

Increasing the Delay Factor, Filter Factor, and the A/D

the amount of current that can flow through the device.

Aperture Time can decrease noisy measurements.

This can be done in the software by setting the Current

• Minimize Noisy Measurements: Noise may be generated

Compliance of each SMU to a safe level, such as 20 µA.

from a variety of sources, including particle collisions,

This is a programmed limit to ensure the current doesn’t

defects, AC pick-up, and electrostatic interference.

exceed the user-defined compliance.

Noisy measurements result when a noise signal is

• Provide Sufficient Settling Time: Because CNT FET

superimposed on the DC signal being measured. This

measurements often involve measuring low current

can result in inaccurate or fluctuating measurements.

(<1 µA), it is important to allow sufficient settling time to

The most common form of external noise “pick-up”

ensure the measurements are stabilized after a current

is 60 Hz (or 50 Hz) line cycle pick-up. This can be a

or voltage has been applied. Some of the factors that

common occurrence near fluorescent lights. Millivolts

affect the settling time of the measurement circuit

of noise are not uncommon. Keithley uses a technique

include the cables, test fixtures, switches, probers,

called Line-Cycle Integration to minimize the effects

the DUT resistance, and the current range of the

of 60 Hz (or 50 Hz) line pick-up. Line-cycle noise will

measurement instrument. To ensure settled readings,

“average out” when the integration time is equal to

additional delay time can be added to the voltage or

an integral number of power line cycles. The number

current step time prior to the measurement. This delay

of power line cycles can be adjusted in the Clarius

time can be easily adjusted in the Test Settings pane

software in the Advanced Test Settings dialog box on

within the Clarius software.

the right side of the screen.

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Electrical Characterization of Carbon Nanotube Transistors

(CNT FETs) with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Electrostatic interference is another cause of noisy

The PMU has two modes of ultra-fast I-V source with

measurements when measuring low currents. This

measure: pulsed I-V and transient I-V. These two modes are

coupling occurs when an electrically charged object

illustrated in Figure 6.

approaches the circuit under test. In high impedance

circuits, this charge doesn’t decay rapidly and can

Samples

result in unstable measurements. The erroneous

readings may be due to either DC or AC electrostatic

fields, so electrostatic shielding will help minimize the

effects of these fields.

Time

The electrostatic shield can be just a simple metal box

Measure Window

that encloses the test circuit. Probe stations often

include an electrostatic/EMI shield or optional dark box.

The shield should be connected to the measurement

circuit LO, which is the Force LO terminal of the SMU.

Pulsed I-V

Transient I-V

The Force LO terminal is the outside shield of the triax

Pulse/Measure with DC-like results

Time-based I and V measurements

cable of the SMU or is located on the GNDU. All cables

Train, Sweep, Step modes

Waveform capture

General device characterization

Dynamic device testing

need to be of a low-noise design and shielded. Each

SMU comes with two low-noise triax cables.

Figure 6. Two modes of ultra-fast I-V source with measure: Pulsed I-V and

Transient I-V.

Keep Probes Up: Make sure the probes are in the up

position (not contacted to the device) when connecting

Pulsed I-V refers to any test with a pulsed source and a

and disconnecting instruments from the terminals

corresponding high speed, time-based measurement

of the device. The process of moving cables has

that provides DC-like results. The current and/or voltage

the potential to inject charge into the device and

measurement is an average of readings taken in a

cause damage. This is due to both triboelectric and

predefined measurement window on the pulse. This average

piezoelectric effects.

of readings is called the “spot mean.” The user defines the

parameters of the pulse, including the pulse width, duty

cycle, rise/fall times, amplitude, etc.

Pulsed I-V Measurements

In addition to making traditional DC I-V measurements,

Transient I-V, or waveform capture, is a time-based

it may be desirable to perform ultra-fast pulsed I-V

current and/or voltage measurement that is typically the

measurements for various reasons. First, it may be

capture of a pulsed waveform. A transient test is typically

important to observe the high speed response of the CNT

a single pulse waveform that is used to study time-varying

device. In some cases, nanostructures can be destroyed

parameters, such as the drain current degradation versus

by the heat generated when making traditional DC

time due to charge trapping or self-heating. Transient I-V

measurements. Pulsed I-V measurements can reduce the

measurements can be used to test a dynamic test circuit

total energy dissipated in a device, and therefore reduce the

or as a diagnostic tool for choosing the appropriate pulse

potential for damage. Finally, pulsed electrical testing can

settings in the pulsed I-V mode.

prevent current drifting in measurements that can occur

Given that the 4225-PMU has two channels, only one module

during DC measurements.

is needed to test a three-terminal CNT FET. A typical test

The pulsed I-V measurements on the CNT FET can be easily

configuration for connecting the PMU module to a CNT

made using the 4225-PMU Ultra-Fast I-V Module. The PMU

FET is shown in Figure 7. In this diagram, Ch 1 of the PMU

provides two channels of high speed, multi-level voltage

is connected to the Gate terminal and Ch 2 is connected to

pulse output while simultaneously measuring current and

the Drain terminal. The Source terminal is connected to the

voltage. This module replaces traditional pulse/measure

PMU Common, which is the outside shield of the PMU coax

test configurations, which consisted of a pulse generator,

connector. To connect this Common terminal to the probe

digital oscilloscope, interconnect hardware, and software.

tip, use a BNC or triax shorting plug that will connect the

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Electrical Characterization of Carbon Nanotube Transistors

(CNT FETs) with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

outside of the coax to the manipulator probe. To generate

capture the current and voltage time-based response to

a V_ds-I_d curve, Ch 1 steps the gate voltage and Ch 2 sweeps

the device. Figure 9 shows the transient response of the

the drain voltage and measures the resulting drain current.

CNT FET. The blue curve is the pulsed drain voltage and the

red curve is the resulting current response as a function

of time.

CNT

The blue voltage output curve looks close to the defined

Source

Drain

rise and fall times of 10µs with a pulse width of 50 µs. Note

SiO2

that the pulse width is measured at one-half of the input

Si Gate

amplitude of 1 V. Therefore, the pulse width is measured

at 500 mV. The sample period in this example is 25 ns

PMU1 CH 2

(40 MHz rate). With proper cabling and connections, the

PMU1 CH 1

Sweeps Drain V

voltage shape should be output as defined by the user with

Steps Gate V

Measures Drain I

minimal deviation.

The red curve shows the drain current and is plotted on

Common

the right Y-axis. The drain current is measured at constant

(outside shield

50 Ω

of PMU

drain and gate voltages. The peaks in the curve are caused

coaxial cable)

by charging and discharging of the cabling, as well as the

current flow through the device. Note that these peaks

CH1

CH2

occur during the pulse transitions. Reducing the pulse

4225-PMU

amplitude or increasing the pulse transition time reduces

the dV/dt, which reduces the peak height.

Figure 7. Circuit diagram for measuring the pulsed I-V characteristics of a

CNT FET.

Optimizing Pulsed I-V Measurements

Figure 8 illustrates a pulsed I-V drain family of curves

To improve the quality of pulsed I-V measurements made

taken with the PMU. For this measurement, a pulse width

with the 4200A-SCS, follow these guidelines:

of 500 µs was used to generate the curves. However,

each PMU channel has the ability to output voltage pulses

• Use the Right Cables and Connections: Using proper

as short as 70 ns with a rise time as short as 20 ns. The

cabling and connections is important for ultra-fast I-V

minimum duration of the pulse width will depend on several

applications in order to achieve the highest frequency

factors, including the test circuit RC time constant and

output and to avoid signal distortions and capacitive

the magnitude of the test current. Each dot on the curves

charging effects.

represents a “spot mean” measurement on the pulsed

- Use cabling and connections optimized for high

waveform.

frequency (at least 150 MHz).

The PMU has five ranges full scale from 800 mA down to

- Use a signal path that matches the impedance of the

100 µA. To measure lower currents, using the 4225-RPM

instrument (50 ohms).

optional Remote Amplifier/Switch is recommended because

- Tie the low side of the DUT to the shield of the PMU

it adds six measurement ranges, down to 100 nA full scale.

coax cable.

The pulsed I-V curves shown in Figure 8 were taken on the

100 µA range. The threshold current was set to 20 µA so that

- Connect the shields from each PMU channel together

the test will stop if the threshold current level is reached.

as close as possible to the DUT.

- Minimize the loop area once the center conductor

For some applications, it may be necessary to study the

and shield are separate in the test circuit.

transient response of a CNT FET. If this is the case, the

- Minimize the cable length.

waveform capture mode (transient I-V) can be used to

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Electrical Characterization of Carbon Nanotube Transistors

(CNT FETs) with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Figure 8. Pulsed I-V drain family of curves of CNT FET.

Figure 9. Waveform of single drain voltage pulse and resulting drain current of CNT FET.

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Electrical Characterization of Carbon Nanotube Transistors

(CNT FETs) with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

• Make the Right Chuck Connections: CNT FETs and

Capacitance-Voltage

other nanotransistors may be either back-gated or top-

Measurements

gated. For back-gated devices, one of the PMU channels

needs to be connected to the chuck of the prober. When

In addition to performing DC and pulsed I-V measurements

making PMU connections to the chuck, the user will

on CNT FETs, measuring the capacitance of the FET can

give up some functionality of the PMU: fast transitions,

also provide information about the device, including the

high frequency, low current, etc. This is because the

mobility, timing effects, and gate dielectrics. Figure 10

output of the high frequency PMU channel is connected

outlines the connections of the 4210-CVU or 4215-CVU

to the chuck capacitance and the chuck cabling, which

to the CNT FET. In this configuration, the gate-to-drain

slows down the source response and couples noise

capacitance is measured as a function of the gate voltage.

into the measurement. If possible, it is better to use a

The HCUR/HPOT terminals that connect the high of the

third manipulator and probe directly to the chuck. For

voltage source to the gate should be connected to the

high speed sourcing and measuring, it is best to use all

chuck. The LCUR/LPOT terminals that measure the

top-side connections and avoid connecting the PMU to

capacitance should be connected to the drain terminal

the chuck.

of the DUT. For best results, the measurement terminals

• Verify Pulse Width: Ensure the pulse width is long

should never be connected to the chuck. For top-gated CNT

enough to ensure a settled reading. Verify the resulting

FETs, both the measure and voltage source can be output to

current measurement is settled by outputting a single

the gate of the FET from the same terminals (either HCUR/

pulse using the Waveform Capture mode. Both the

HPOT or LPOT/LCUR) of the CVU. The HI and LO terminals

current and voltage can be plotted as a function of time

of the CVU are interchangeable in the Terminal Settings

in the Graph.

window of the CVU in the Clarius software. The results of

• Minimize Noise: To minimize noisy results, multiple

generating a C-V sweep between the gate and drain of the

waveforms can be averaged or a moving average

CNT FET are shown in Figure 11.

function can be created in the built-in Formulator to

smooth out the measurements further.

CVU

HCUR

Source

CNT

Source

Drain

HPOT

SiO2

Si Gate

Ammeter

LPOT

ABB

Feedback

LCUR

Voltmeter

Figure 10. Connections of the CVU to a CNT FET.

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Electrical Characterization of Carbon Nanotube Transistors

(CNT FETs) with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Figure 11. C-V sweep of gate-to-drain capacitance.

Optimizing Capacitance Measurements

• Choose Appropriate Hold and Sweep Delay Times: The

condition of a device when all internal capacitances are

To improve the quality of capacitance measurements made

fully charged after an applied voltage step is referred

with the CVU, follow these guidelines:

to as “equilibrium.” If capacitance measurements are

• Perform Open Compensation (for Measurements

made before the device is in equilibrium, inaccurate

<10 pF): The open correction feature compensates for

results may occur.

capacitance offsets in the cabling and connections.

To choose the delay times for a C-V sweep, step an

Performing the correction is a two-part process. The

applied voltage using the Sampling Mode, and plot the

corrections are performed, and then they are enabled

capacitance as a function of time. Observe the settling

within a test module.

time from the graph. Use this time for the Hold Time for

To perform the corrections, select Tools at the top of

the initial applied voltage or for the Sweep Delay Time

the screen and select CVU Connection Compensation.

applied at each step in the sweep. The Sweep Delay

For an Open correction, select Measure Open. Probes

Time may not need to be as long as the first step. The

must be up or the DUT removed from the test fixture.

user will need to experiment to verify the appropriate

Enable the correction by selecting Open Compensation

time.

button in the Terminal Settings pane.

• Choose Appropriate Speed Mode in the Test Settings

• Use Proper Shield Connections: Connect the shields

window: The Speed mode function enables the user

of the coax cables together as close as possible to the

to adjust the time for settling and integration of the

DUT. This reduces the loop area of the shields, which

measurement. For small capacitances (pico-Farads

minimizes the inductance. This also helps to maintain

or less) use the Quiet or Custom Speed modes for

the transmission line effects. If the shields are not

best results.

connected together, offsets may occur. The higher the

frequency, the more important this becomes.

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Electrical Characterization of Carbon Nanotube Transistors

(CNT FETs) with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

• Use Guarding: When making very small capacitance

Conclusion

measurements, guarding will help prevent stray

When using the appropriate instrumentation

capacitance from unused terminals of the device from

and measurement techniques, optimal electrical

affecting measurement accuracy. For example, if

characterization of CNT FETs can be achieved. The

measuring the capacitance between only the gate and

4200A-SCS is an ideal tool for performing electrical

drain terminals, the source terminal of the FET can be

characterization of CNT FETs and other nanostructures

connected to the guard. The guard terminal of the CVU

because of its integrated hardware, software, and analysis

is the outside shield of the coax cable.

tools. The SMUs can be used to determine V_ds-I_d, V_GS-I_d,

resistance, and other I-V measurements on the CNT FET.

The PMU can be used to make pulsed I-V measurements

or observe the transient response of a pulsed waveform

applied to the DUT. The CVU can be used to generate C-V,

C-f, or C-t curves. Using the Carbon Nanotube Transistor

Characterization (cntfet) project that comes with the

4200A-SCS can further simplify measurement setup

and execution.

Acknowledgement

The author appreciates the assistance provided by Sandia

National Labs, Livermore, California, who supplied the

CNT FETs used in the device testing process during the

development of this application note.

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DC I-V and AC

Impedance Testing of

Organic FETs

DC I-V and AC Impedance Testing of Organic FETs

APPLICATION NOTE

Introduction

Drain

Source

Organic semiconductor devices have been developed

as replacements for traditional semiconductor devices

Organic Semiconductor

because they use lower cost materials, are less expensive

to manufacture, can be printed onto surfaces such as paper

Dielectric

and glass, and can be used in flexible circuit designs. These

Gate

devices are used in a range of applications that includes

displays, medical devices, lighting, sensors, memory

Figure 1. Bottom-gated organic field effect transistor.

devices, batteries, and solar cells. One of the most common

organic semiconductor devices is the Organic Field Effect

Transistor (OFET).

Making Electrical Measurements

with the 4200A-SCS

OFET research generally seeks to optimize the performance

of the device, such as its carrier mobility and on/off

The 4200A-SCS system includes tests for making some

current ratio. DC I-V techniques are used to determine the

of the most commonly used electrical measurements

output and transfer characteristics, hysteresis effects,

on organic FETs. These tests for making DC I-V, very low

bias stressing, gate leakage current, etc. AC impedance

frequency C-V, and high frequency C-V measurements can

techniques can reveal critical information about the device,

be found in the Test Library by searching on the keyword

like its carrier mobility, threshold voltage, flat band voltage,

“ofet” or “organic” while in the Select view of the Clarius

and charge effects.

software. All these tests can also be found in the Organic

FET Characterization Project (ofet) in the Project Library

This application note outlines how to optimize DC I-V

using the keyword, “ofet” or “organic” in the Search field.

and AC impedance measurements on OFETs using the

Figure 2 shows a screen capture of this project. In addition

4200A-SCS Parameter Analyzer. Timing parameters, noise

to the provided tests, the user can also easily create their

reduction, shielding, proper cabling, and other important

own tests and projects based on their application and

measurement considerations for achieving the best results

measurement requirements.

will be discussed.

The Organic Field Effect Transistor

(OFET)

The OFET is a type of field effect transistor that uses an

organic semiconductor material as the channel between

the source and drain terminals of the device. The organic

thin film transistor (OTFT) is a type of OFET; for this

application note, these two FETs will be used synonymously.

Figure 1 illustrates a bottom-gated OFET. The organic

semiconductor is placed above a dielectric that sits above

Figure 2. Screen capture of Organic FET Characterization Project.

the gate terminal. Two metal contacts are located across

the top of the organic semiconductor for the source and

drain terminals. Connections are made to the three device

terminals to perform the electrical measurements.

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DC I-V and AC Impedance Testing of Organic FETs

APPLICATION NOTE

Current-Voltage Measurements

The I-V characteristics of an organic device can be used

to extract many of the device’s parameters, study the

effects of fabrication processes, and determine the

quality of the contacts. The Test Library and Organic FET

Characterization project includes tests to measure the

output characteristics (I_D-V_DS) and transfer characteristics

(I_D-V_GS) of an OFET.

Figure 3 illustrates a DC I-V test configuration for measuring

the transfer characteristics of an OFET using two SMUs

(4200-SMU, 4201-SMU, 4210-SMU or 4211-SMU) with optional

4200-PA preamps. These SMUs are capable of sourcing and

measuring both current and voltage. They have pico-amp

Figure 4. ID-VGS curve of an OFET.

sensitivity and can be current-limited to prevent damage to

the device. In this diagram, SMU1 is connected to the gate of

The SMUs connected to each terminal of the OFET can

the OFET and SMU2 is connected to the drain terminal. The

be easily reconfigured in the Clarius software to perform

source terminal is connected to the ground unit (GNDU) or it

other tests. The output characteristics, I_D vs. V_D, can

can be connected to a third SMU if it is necessary to source

also be measured by changing the SMU parameters in the

and measure from all three terminals of the OFET.

software. It’s also possible to use the preconfigured Organic

FET Output Characteristics (ofet-id-vds) test in the Test

Drain

Source

Force LO

Library. By stepping the gate voltage and measuring the

Organic Semiconductor

Force HI

Dielectric

drain current as a function of drain voltage, a drain family

SMU2

Ground Unit or SMU3

Gate

(if required)

Applies Drain

of curves can be generated. Figure 5 shows the results of

Voltage (VD),

Force HI

Measures

measuring I_D-V_DS curves of a p-type OFET using the ofet-id-

Drain Current

SMU1

(ID)

vds test.

Sweeps Gate

Voltage (VG)

Figure 3. Circuit diagram for measuring the DC I-V characteristics of an OFET.

Once the SMUs are connected to the OFET, the transfer

characteristics can be generated using the Organic FET

Drain Current vs. Gate Voltage (ofet-id-vgs) test in the

Test Library. In this test, SMU2 applies a constant drain

voltage (V_D) and measures the drain current (I_D) while SMU1

sweeps the gate voltage (V_G). Figure 4 shows the results

of measuring the drain current as a function of the gate

voltage of an OFET. The hysteresis sweep is performed

using the Dual Sweep function in the software. Notice the

Figure 5. Output Characteristics of a p-type OFET.

many decades of current-from femto-amps to milli-amps-

that the SMUs with preamps can measure.

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DC I-V and AC Impedance Testing of Organic FETs

APPLICATION NOTE

integral number of power line cycles. This A/D aperture time

Optimizing DC I-V Measurements

(measurement window) can be adjusted using the Speed

The following techniques will improve the quality of DC

setting in the Test Settings pane.

measurements made on organic FETs with the 4200A-SCS:

Electrostatic interference is another cause of noisy

Eliminate Lead and Contact Resistance: The series

measurements when measuring low currents. This coupling

resistance of the cables used to connect the SMU to the

occurs when an electrically charged object approaches

device can cause measurement errors. The effects of

the circuit under test. In high impedance circuits, this

the cable resistance are particularly detrimental when

charge doesn’t decay rapidly and can result in unstable

using long connecting cables and high currents because

measurements. The erroneous readings may be due

the voltage drop is significant compared to the measured

to either DC or AC electrostatic fields, so electrostatic

voltage.

shielding will help minimize the effects of these fields.

As shown in Figure 6, the voltage drop due to the cable

An electrostatic shield can be just a simple metal box that

resistance is added to the voltage measurement of a DUT

encloses the test circuit. However, this can be difficult

when making 2-wire, or local sense, connections. In this

when working within a laboratory glove box, which is often

case, the current flows across both cables, as well as the

used with organic devices. Probe stations often include an

DUT, causing three voltage drops that all are measured by

electrostatic/EMI shield or optional dark box. As shown in

the SMU voltmeter. To eliminate the cable resistance from

Figure 7, the shield surrounds the device and is connected

the measurement, a 4-wire or remote sense connection is

to the measurement circuit LO, which is the Force LO

made to the device, as shown in the right half of Figure 6. In

terminal of the SMU. The Force LO terminal is the outside

this case, only the voltage drop across the DUT is measured

shield of the triax cable of the SMU and is also located on the

by the SMU voltmeter.

rear panel of the 4200A-SCS in the ground unit (GNDU). All

cables need to be low noise and shielded. Each SMU comes

2-Wire, Local Sense

4-Wire, Remote Sense

with two low noise triax cables.

SMU

Force HI

SMU

Force HI

RCable

R Cable

Sense HI

R Cable

SMU

Force HI

DUT

Sense LO

Conductive

RCable

R Cable

Shield

Force LO

R Cable

Measured Voltage:

VM = VDUT + 2RCable

VM = VDUT

Figure 6. Local vs. Remote Sense.

Force

Minimize Noise in Measurements: Noise may be generated

from a variety of sources, including AC pickup and

electrostatic interference. Noisy measurements result

Figure 7. Conductive Shield Surrounds Device Under Test.

when a noise source is superimposed on the DC signal

being measured. This can result in inaccurate or fluctuating

Provide Sufficient Settling Time: Because device leakage

measurements.

current usually involves measuring very low current (<1 nA),

it is important to allow sufficient settling time to ensure the

The most common form of external noise pickup is 60

measurements are stabilized after a voltage bias has been

Hz (or 50 Hz) line cycle pickup. This can be a common

applied. Some of the factors that affect the settling time of

occurrence near fluorescent lights. Millivolts of noise are

the measurement circuit include the cables, test fixtures,

not uncommon. Keithley uses a technique called Line-

switches, probers, the DUT resistance and capacitance, and

Cycle Integration to minimize the effects of 60 Hz (or 50 Hz)

the current range of the SMU. To ensure settled readings,

line pickup. Line-cycle noise will average out when the

integration time, or measurement window, is equal to an

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DC I-V and AC Impedance Testing of Organic FETs

APPLICATION NOTE

additional delay time can be added to the voltage step prior

Because the very low frequency method works only over

to the measurement. This delay time can be easily adjusted

a limited frequency range, the capacitance of the device

in the Test Settings pane in the Clarius software.

under test (DUT) should be in the range of 1 pF to 10 nF.

Table 1 summarizes the VLF C-V specifications. Complete

specifications and more detailed information about this

Very Low Frequency

technique can be found in a Keithley application note,

Capacitance-Voltage Technique

“Performing Very Low Frequency Capacitance-Voltage

In addition to measuring very small currents, two SMUs

Measurements of High Impedance Devices Using the

with preamps can be used to measure Very Low Frequency

4200A-SCS Parameter Analyzer.”

C-V (VLF C-V). C-V sweeps and C-t measurements can be

Table 1. Typical Measurement Accuracy

made with test frequencies from 10 mHz to 10 Hz. Figure 8

Measured

C Accuracy @

is a simplified diagram of the two-SMU configuration used

Frequency

Capacitance

300 mV rms¹

30 mV rms¹

to generate low frequency impedance measurements.

1 pF

10%

13%

This configuration requires a 4200A-SCS Parameter

10 pF

10%

Analyzer with two SMUs and two 4200-PA preamps with

10 Hz

100 pF

one connected to either side of the device under test. SMU1

outputs the DC bias with a superimposed AC signal and

1 nF

measures the voltage. SMU2 measures the resulting AC

10 nF

current while sourcing 0V DC.

1 pF

10 pF

Capacitor

1 Hz

100 pF

1 nF

Test Device

10 nF

Force HI

1 pF

SMU1

SMU2

smu_src

smu_sense

10 pF

100 mHz

100 pF

1 nF

Force LO

10 nF

(Internally Connected)

1 pF

10%

SMU1 with preamp:

SMU2 with preamp:

Outputs DCV with

Measures AC current

10 pF

superimposed ACV and

at 0 V DC.

measures AC voltage.

10 mHz

100 pF

1 nF

Figure 8. Connections for Very Low Frequency C-V measurements.

10 nF

While the voltage is forced, voltage and current

NOTES

measurements are obtained simultaneously over several

±20V maximum includes the DC Bias and the AC Test Signal peak voltage. Maximum

negative bias voltage = -20 + (AC voltage *

). Maximum positive bias voltage = 20 -

cycles. The magnitude and phase of the DUT impedance

(AC voltage *

is extracted from the discrete Fourier transform (DFT)

2. Test device must have dissipation factor D_X <0.1. All data shown for DC Bias voltage = 0V.

of a ratio of the resultant voltage and current sinusoids.

All specifications apply at 23°C ±5°C, within one year of calibration, RH between 5% and 60%,

after 30 minutes of warmup.

The narrow-band information can be collected at varying

frequencies (10 mHz to 10 Hz) to measure the complex

impedance of the DUT. The resulting output parameters

include the impedance (Z), phase angle (θ), capacitance

(C), conductance (G), resistance (R), reactance (X), and the

dissipation factor (D).

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DC I-V and AC Impedance Testing of Organic FETs

APPLICATION NOTE

VLF C-V Characterization

High Frequency Capacitance-

of Organic FETs

Voltage Measurements

The built-in software for performing VLF C-V measure-

In addition to DC I-V and VLF C-V measurements, measuring

ments can be used on different types of devices, including

the capacitance of an OFET can provide information about

organic FETs and MIS capacitor devices. Figure 9 shows the

the device, including the gate capacitance and the carrier

results of performing a C-V sweep with a test frequency of

mobility. Figure 10 shows the connections of the 4210-CVU

0.25 Hz on an OFET between the gate and drain terminals

or 4215-CVU Capacitance Voltage Unit to an OFET. In this

using the Organic FET Very Low Frequency C-V Sweep (ofet-

configuration, the gate-to-drain capacitance is measured

vlf-cv) test in the Test Library.

as a function of the gate voltage.

CVU

HCUR

Source

Drain

Source

HPOT

Organic Semiconductor

Volt

Dielectric

meter

Gate

LPOT

Chuck

ABB

Feedback

LCUR

Ammeter

Figure 10. Connections from the CVU to an OFET.

Using the Organic FET C-V Sweep (ofet-hf-cv) test in the

Test Library, a C-V sweep from -10 V to 10 V at 50 kHz

was generated on an OFET between the gate and drain

terminals. The results of the C-V sweep are shown in

Figure 11.

Figure 9. A Very Low Frequency C-V Sweep of an OFET at a Test Frequency of

0.25 Hz.

Figure 11. High Frequency C-V Sweep of an OFET.

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DC I-V and AC Impedance Testing of Organic FETs

APPLICATION NOTE

Sampling Operation Mode. The observed time can also be

Optimizing Capacitance

used for the Sweep Delay time applied for each step in the

Measurements

sweep. The Sweep Delay time may not need to be as long

To improve the quality of capacitance measurements

as the Hold Time. The user will need to experiment to verify

made with the 4200A-SCS, follow these guidelines:

the appropriate times to use in the Test Settings pane for a

particular test.

Perform Open Compensation (for measurements <10 pF):

The open correction feature compensates for capacitance

Use Proper Shield Connections: When measuring AC

offsets in the cabling and connections. Performing the

impedance at test frequencies greater than 1 MHz,

correction is a two-part process. The corrections are

connect the shields of the coax cables together as close

performed, and then they are enabled within a test.

as possible to the device. This reduces the loop area of the

shields, which minimizes the inductance. This also helps to

To perform the corrections in the Clarius software, select

maintain the transmission line effects. If the shields are not

Tools at the top of the screen and select CVU Connection

connected together, offsets may occur.

Compensation. For an Open correction, select Measure

Open. Probes must be up or the DUT removed from the test

Choose the Appropriate Speed Mode in the Test Settings

fixture. Once the correction data is acquired from the Tools

Window: The Speed Mode function allows adjusting the

menu, the correction is enabled within a test by selecting

settling time and measure window (A/D aperture) of the

Open Compensation in the Terminal Settings pane.

measurements. For small capacitances, use the Quiet or

Custom Speed modes for best results.

Choose Appropriate Hold and Sweep Delay Times: The

condition of a device when all internal capacitances are

fully charged after an applied voltage step is referred to

Conclusion

as “equilibrium.” If capacitance measurements are made

Appropriate instrumentation and measurement

before the device is in equilibrium, the results of these

techniques make it possible to achieve optimal electrical

measurements may be inaccurate.

characterization of organic FETs. The 4200A-SCS is an ideal

tool for performing electrical characterization of OFETs

To choose the appropriate delay times, apply DC voltage

because of its integrated hardware, interactive software,

to the device using the Sampling Test Mode, and plot the

and analysis capabilities. The test system includes built-

capacitance as a function of time. Observe the settling

in tools, such as open correction, informational videos,

time from the graph. This observed equilibrium time can

the Help function, and timing controls to help researchers

be used as the Hold Time, which is the time the Presoak

minimize set-up time and achieve the best measurement

Voltage is output prior to the beginning of the Sweep or

results as quickly as possible.

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Electrical Characterization

of Photovoltaic Materials and

Solar Cells with the 4200A-SCS

Parameter Analyzer

I-V, C-V, C-f, DLCP, Pulsed I-V, Resistivity, and Hall Voltage

Measurements

Electrical Characterization of Photovoltaic Materials and

Solar Cells with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Introduction

Making Electrical Measurements

The increasing demand for clean energy and the largely

with the 4200A-SCS

untapped potential of the sun as an energy source is

To simplify testing photovoltaic materials and cells, the

making solar energy conversion technology increasingly

4200A-SCS is supported with tests and a project for making

important. As a result, the demand for solar cells, which

many of the mostly commonly used measurements easily.

convert sunlight directly into electricity, is growing. Solar

These tests, which include I-V, capacitance, and resistivity

or photovoltaic (PV) cells are made up of semiconductor

measurements, also include formulas for extracting

materials that absorb photons from sunlight and then

common parameters such as the maximum power, short

release electrons, causing an electric current to flow when

circuit current, defect density, etc. The SolarCell project

the cell is connected to a load. A variety of measurements

(Figure 1) is included with all 4200A-SCS systems and can

are used to characterize a solar cell’s performance,

be found in the Project Library if you use the PV cell filter.

including its output and its efficiency. This electrical

Most of the tests in this project can also be found in the Test

characterization is performed as part of research and

Library.

development of photovoltaic cells and materials, as well as

during the manufacturing process.

Table 1. Tests in the SolarCell project

Measurement

Name

Description

Some of the electrical tests commonly performed on

Performs I-V sweep and calculates

solar cells involve measuring current and capacitance

fwd-ivsweep

I_sc, V_oc, P_max, I_max, V_max, FF

DC I-V

as a function of an applied DC voltage. Capacitance

rev-ivsweep

Performs reversed bias I-V sweep

measurements are sometimes made as a function of

solarcell-cvsweep

Generates C-V sweep

frequency or AC voltage. Some tests require pulsed

Generates C-V sweep and calculates

current-voltage measurements. These measurements are

solarcell-c-2vsv

1/C²

usually performed at different light intensities and under

Sweeps the frequency and measures

cfsweep

different temperature conditions. A variety of important

Capacitance

capacitance

device parameters can be extracted from the DC and

Measures capacitance as AC voltage

is swept. DC voltage is applied so

pulsed current-voltage (I-V) and capacitance-voltage

dlcp

as to keep the total applied voltage

constant. The defect density is

(C-V) measurements, including output current, conversion

calculated.

efficiency, maximum power output, doping density,

solarcell-pulse-

Performs pulse I-V sweep using one

Pulse-IV

resistivity, etc. Electrical characterization is important in

iv-sweep

channel of PMU

determining how to make the cells as efficient as possible

Uses 3 or 4 SMUs to source current

and measure voltage difference

with minimal losses.

hir

for high resistance semiconductor

materials. Calculates sheet

Instrumentation such as the 4200A-SCS Parameter

resistivity.

4-Probe

Analyzer can simplify testing and analysis when making

Resistivity

Uses 1 or 2 SMUs to source current

and measure voltage using remote

these critical electrical measurements. The 4200A-SCS

sense. Calculates sheet resistivity.

lor

is an integrated system that includes instruments for

Uses current reversal method to

compensate for thermoelectric

making DC and ultra fast I-V and C-V measurements, as

voltage offsets.

well as control software, graphics, and mathematical

First of 4 tests that are used to

measure the van der Pauw resistivity.

analysis capability. The 4200A-SCS is well-suited for

This test sources current between

i1-v23

performing a wide range of measurements, including DC

terminals 1 and 4 and measures the

voltage difference between terminals

and pulsed current-voltage (I-V), capacitance-voltage

2 and 3.

(C-V), capacitance-frequency (C-f), drive level capacitance

Sources current between terminals

profiling (DLCP), four-probe resistivity (ρ, σ), and Hall

i2-v34

2 and 1 and measures the voltage

vdp Resistivity

difference between terminals 3 and 4.

voltage (V_H) measurements. This application note describes

Sources current between terminals

how to use the 4200A-SCS to make these electrical

i3-v41

3 and 2 and measures the voltage

measurements on PV cells.

difference between terminals 4 and 1.

Sources current between terminals

i4-v12

4 and 1 and measures the voltage

difference between terminals 1 and 2.

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Electrical Characterization of Photovoltaic Materials and

Solar Cells with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Figure 1. Screenshot of Solar Cell project for the 4200A-SCS

DC Current-Voltage (I-V)

Parameters Derived from I-V

Measurements

A solar cell may be represented by the equivalent circuit

As described previously, many solar cell parameters can

model shown in Figure 2, which consists of a light-induced

be derived from current-voltage (I-V) measurements of

current source (I_L), a diode that generates a saturation

the cell. These I-V characteristics can be measured using

current [I_S(e^qV/kT -1)], series resistance (r_s), and shunt

the 4200A-SCS’s Source-Measure Units (SMUs), which can

resistance (r_sh). The series resistance is due to the

source and measure both current and voltage. Because

resistance of the metal contacts, ohmic losses in the front

these SMUs have four-quadrant source capability, they can

surface of the cell, impurity concentrations, and junction

sink the cell current as a function of the applied voltage.

depth. The series resistance is an important parameter

Four types of SMUs are available for the 4200A-SCS: the

because it reduces both the cell’s short-circuit current and

4200-SMU or 4201-SMU, which can source/sink up to

its maximum power output. Ideally, the series resistance

100 mA, and the 4210-SMU or 4211-SMU, which can source/

should be 0 Ω (r_s = 0). The shunt resistance represents the

sink up to 1 A. If the output current of the cell exceeds these

loss due to surface leakage along the edge of the cell or

current levels, it may be necessary to reduce it, possibly

to crystal defects. Ideally, the shunt resistance should be

by reducing the area of the cell itself. However, if this is not

infinite (r_sh = ∞).

possible, Keithley’s SourceMeter^® instruments, which are

capable of sourcing/sinking higher currents, offer possible

alternative solutions.

PV Cell

r_s

Photon hυ

I_L

r_sh

Load

R_L

Figure 2. Idealized equivalent circuit of a photovoltaic cell

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Electrical Characterization of Photovoltaic Materials and

Solar Cells with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

If a load resistor (R

) is connected to an illuminated solar

As defined, the fill factor is the ratio of the maximum power

cell, then the total current becomes:

(P_max = I_maxV_max) to the product of the short circuit current

). The ideal solar cell

(I_sc) and the open circuit voltage (V_oc

I = I_S(e^qV/kT - 1) - I_L

has a fill factor equal to one (1) but losses from series and

shunt resistance decrease the efficiency.

where:

I_S = current due to diode saturation

Another important parameter is the conversion efficiency

(η), which is defined as the ratio of the maximum power

I_L = current due to optical generation

output to the power input to the cell:

Several parameters are used to characterize the efficiency

P_max

______

η =

of the solar cell, including the maximum power point (P_max),

P_in

the energy conversion efficiency (η), and the fill factor (FF).

where:

These points are illustrated in Figure 3, which shows a

typical forward bias I-V curve of an illuminated PV cell. The

P_max = the maximum power output (W)

maximum power point (P_max) is the product of the maximum

P_in = the power input to the cell defined as the total radiant

cell current (I_max) and the voltage (V_max) where the power

energy incident on the surface of the cell (W)

output of the cell is greatest. This point is located at the

“knee” of the curve.

Making Connections to the Solar Cell for

I-V Measurements

I_sc

P_max

200

Figure 4 illustrates a solar cell connected to the 4200A-SCS

max

for I-V measurements. One side of the solar cell is

150

connected to the Force and Sense terminals of SMU1; the

other side is connected to the Force and Sense terminals of

100

Maximum Power Area

either SMU2 or the ground unit (GNDU) as shown.

P_max = I_maxV_max

SMU1

Force HI

0.0

0.2

0.4

0.6

0.8

Cell Voltage (V)

Vmax Voc

Sense HI

Figure 3. Typical forward bias I-V characteristics of a PV cell

V-Source

Solar Cell

The fill factor (FF) is a measure of how far the I-V

Sense LO

characteristics of an actual PV cell differ from those of an

ideal cell. The fill factor is defined as:

Force LO

I_maxV_max

__________

FF =

SMU2 or GNDU

I_scV_oc

where:

Figure 4. Connection of 4200A-SCS to a solar cell for I-V measurements

I_max = the current at the maximum power output (A)

Using a four-wire connection eliminates the lead resistance

Vmax = the voltage at the maximum power output (V)

that would otherwise affect this measurement’s accuracy.

With the four-wire method, a voltage is sourced across

I_sc = the short-circuit current (A)

the solar cell using one pair of test leads (between Force

Voc = the open-circuit voltage (V)

HI and Force LO), and the voltage drop across the cell is

measured across a second set of leads (across Sense HI

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Electrical Characterization of Photovoltaic Materials and

Solar Cells with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Figure 5. Results of calculated parameters shown in the Sheet in the Analyze pane.

and Sense LO). The sense leads ensure that the voltage

shows some of the derived parameters in the Sheet. These

developed across the cell is the programmed output value

parameters include the short-circuit current (I_SC), the open

and compensate for the lead resistance.

circuit voltage (V_OC), the maximum power point (P_max), the

maximum cell current (I_max), the maximum cell voltage

(V_max), and the fill factor (FF).

Forward-Biased I-V Measurements

The user can easily add other formulas depending on the

Forward-biased I-V measurements of the solar cell are

required parameters that need to be determined.

made under controlled illumination. The SMU is set up to

output a voltage sweep and measure the resulting current.

Using the Formulator, the conversion efficiency (η) can also

This forward bias sweep can be performed using the

be calculated if the user knows the power input to the cell

Solar Cell Forward I-V Sweep or “fwd-ivsweep” test, which

and inputs the formula. The current density (J) can also be

allows adjusting the sweep voltage to the desired values.

derived by using the Formulator and inputting the area of

As previously illustrated in Figure 3, the voltage source is

the cell.

swept from V₁ = 0 to V₂ = V_OC. When the voltage source is 0

(V₁ = 0), the current is equal to the source-circuit current

Figure 6 shows an actual I-V sweep of an illuminated silicon

(I₁ = I_SC). When the voltage source is an open circuit (V₂ = V_OC)

PV cell generated with the 4200A-SCS using the “fwd-

then the current is equal to zero (I₂ = 0). The parameters,

ivsweep” test. Because the system’s SMUs can sink current,

V_OC and I_SC can be derived easily from the sweep data using

the curve passes through the fourth quadrant and allows

the 4200A-SCS’s built-in mathematical analysis tool, the

power to be extracted from the device (I-, V+). If the current

Formulator. For convenience, the Solar Cell Forward I-V

output spans several decades as a function of the applied

Sweep test has the commonly derived parameters already

voltage, it may be desirable to generate a semilog plot of

calculated, so the values automatically appear in the Sheet

I vs. V. The Graph supports an easy transition between

in the Analyze pane every time the test is executed. Figure 5

displaying data graphically on either a linear or a log scale.

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Electrical Characterization of Photovoltaic Materials and

Solar Cells with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

By using additional light intensities, this technique can be

extended using multiple points located near the knee of the

curves. As illustrated in Figure 8, a line is generated from

which the series resistance can be calculated from the

slope.

When considered as ammeters, one important feature

of the SMUs is their very low voltage burden. The voltage

burden is the voltage drop across the ammeter during

the measurement. Most conventional digital multimeters

(DMMs) will have a voltage burden of at least 200 mV at

full scale. Given that only millivolts may be sourced to the

sample in solar cell testing, this can cause large errors.

The 4200A-SCS’s SMUs don’t produce more than a few

hundred microvolts of voltage burden, or voltage drop, in

the measurement circuit.

Figure 6. I-V sweep of silicon PV cell generated with the 4200-SMU

If desired, the graph settings functions make it easy to

create an inverted version of the graph about the voltage

axis. Simply go to the Graph Settings tab, select Axis

Properties, select the Y1 Axis tab, and click on the Invert

checkbox. The inverse of the graph will appear as shown in

∆V

r_S =

Figure 7.

∆I

Voltage (V)

Figure 8. Slope method used to calculate the series resistance

Reverse-Biased I-V Measurements

The leakage current and shunt resistance (r_sh) can be

derived from the reverse-biased I-V data. Typically, the test

is performed in the dark. The voltage is sourced from 0V to

a voltage level where the device begins to break down. The

resulting current is measured and plotted as a function of

Figure 7. Inversion of the forward-biased I-V curve about the voltage axis

the voltage. Depending on the size of the cell, the leakage

current can be as small as picoamps. The SMUs have a

The series resistance (r_s) can be determined from the

preamp option that allows making accurate measurements

forward I-V sweep at two or more light intensities. First,

well below a picoamp. When making very sensitive low

make I-V curves at two different intensities (the magnitudes

current measurements (nanoamps or less), use low noise

of the intensities are not important). Measure the slope of

cables and place the device in a shielded enclosure to shield

this curve from the far forward characteristics where the

it electrostatically. This conductive shield is connected

curve becomes linear. The inverse of this slope yields the

to the Force LO terminal of the 4200A-SCS. The Force LO

series resistance:

terminal connection can be made from the outside shell

∆V

of the triax connectors, the black binding post on the

____

rs⁼

∆I

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Electrical Characterization of Photovoltaic Materials and

Solar Cells with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

ground unit (GNDU), or from the Force LO triax connector on

Capacitance Measurements

the GNDU.

Capacitance-voltage measurements are useful in deriving

One method for determining the shunt resistance of the

particular parameters about PV devices. Depending on the

PV cell is from the slope of the reverse-biased I-V curve, as

type of solar cell, capacitance-voltage (C-V) measurements

shown in Figure 9. From the linear region of this curve, the

can be used to derive parameters such as the doping

shunt resistance can be calculated as:

concentration and the built-in voltage of the junction. A

capacitance-frequency (C-f) sweep can be used to provide

∆V_{Reverse Bias}

rsh =_______________

information on the existence of traps in the depletion

∆I_{Reverse Bias}

region. The 4210-CVU or 4215-CVU, the 4200A-SCS’s

optional capacitance meter, can measure the capacitance

V_{Reverse Bias}

as a function of an applied DC voltage (C-V), a function of

frequency (C-f), a function of time (C-t), or a function of

the AC voltage. The CVU can also measure conductance

ΔI_{Reverse Bias}

and impedance.

ΔV_{Reverse Bias}

To make capacitance measurements, a solar cell is

ΔV_{Reverse Bias}

connected to the CVU as shown in Figure 11. Like I-V

r_sh ≈

log I_{Reverse Bias}

ΔI_{Reverse Bias}

measurements made with the SMU, the capacitance

measurements also involve a four-wire connection to

Figure 9. Typical reverse-biased characteristics of a PV cell

compensate for lead resistance. The HPOT/HCUR terminals

are connected to the anode and the LPOT/LCUR terminals

Figure 10 shows an actual curve of a reverse-biased solar

are connected to the cathode. This connects the high DC

cell, generated using the Solar Cell Reverse I-V Sweep or

voltage source terminal of the CVU to the anode.

“rev-ivsweep” test. In this semi-log graph, the absolute value

of the current is plotted as a function of the reverse-biased

CVU

voltage that is on an inverted x-axis.

HCUR

Source

HPOT

Solar

Volt-

Cell

meter

LPOT

ABB

Feedback

LCUR

Ammeter

Figure 11. Connecting the solar cell to the CVU capacitance meter

Figure 11 shows the shields of the four coax cables

coming from the four terminals of the capacitance meter.

Figure 10. Reverse-biased I-V measurement of silicon solar cell using the SMU

The shields from the coax cables must be connected

together as close as possible to the solar cell to obtain

the highest accuracy because this reduces the effects of

the inductance in the measure circuit. This is especially

important for capacitance measurements made at higher

test frequencies.

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Electrical Characterization of Photovoltaic Materials and

Solar Cells with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Performing an Open and Short Connection Compensation

______________________

N(a) =

will reduce the effects of cable capacitance on

qE_SA²[d(1/C²)/dV]

measurement accuracy. This simple procedure is described

where:

in the 4200A-SCS Reference Manual.

N(a) = the doping density (1/cm³)

Given that the capacitance of the cell is directly related to

the area of the device, it may be necessary to reduce the

q = the electron charge (1.60219 × 10^-19C)

area of the cell itself, if possible, to avoid capacitances

E_S = semiconductor permittivity (1.034 × 10^-12F/cm for

that may be too high to measure. Also, setting the CVU to

silicon)

measure capacitance at a lower test frequency and/or lower

AC drive voltage will allow measuring higher capacitances.

A = area (cm²)

C = measured capacitance (F)

C-V Sweep

V = applied DC voltage (V)

C-V measurements can be made either forward-biased or

reverse-biased. However, when the cell is forward-biased,

The built-in voltage of the cell junction can be derived

the applied DC voltage must be limited; otherwise, the

from the intersection of the 1/C² curve and the horizontal

conductance may get too high for the capacitance meter to

axis. This plot should be a fairly straight line. An actual

measure. The maximum DC current cannot be greater than

curve taken with the CVU, generated using the Solar

10 mA; otherwise, the instrument’s DC voltage source will go

Cell I/C² C-V Sweep or “solarcell-c-2vsv” test, is shown in

into compliance and the DC voltage output will not be at the

desired level.

Figure 13. The Formulator function is used to derive both

the doping density (N) and the built-in voltage on the x-axis

Figure 12 illustrates a C-V curve of a silicon solar cell

(x-intercept). The doping density is calculated as a function

generated by the CVU using the Solar Cell C-V Sweep or

of voltage in the Formulator and appears in the Sheet in the

“solarcell-cvsweep” test. This test was performed in the dark

Analyze pane. The user must input the area of the cell in

while the cell was reversed-biased.

the Constants area of the Formulator. The built-in voltage

source value is derived both in the Formulator and by using

a Linear Line Fit option in the Graph settings. Notice the

value of the x-intercept appears in the lower left corner of

the graph.

Figure 12. C-V sweep of a silicon solar cell

Rather than plotting dC/dV, it is sometimes desirable to view

the data as 1/C² vs. voltage because some parameters are

related to the 1/C² data. For example, the doping density

(N) can be derived from the slope of this curve because N is

related to the capacitance by:

Figure 13. 1/C² vs. voltage of a silicon solar cell

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APPLICATION NOTE

Thus, in DLCP, the position (x_e) can be varied by adjusting the

C-f Sweep

DC voltage bias to the sample. This also allows determining

The CVU option can also measure capacitance,

the defect density as a function of the distance, or special

conductance, or impedance as a function of the test

profiling. The test frequency and temperature of the

frequency. The range of frequency is from 1 kHz to 10 MHz.

measurement can also be varied to show a profile that is

The curve in Figure 14 was generated by using the Solar

energy dependent.

Cell C-f Sweep or “cfsweep” test. Both the range of sweep

frequency and the bias voltage can be adjusted. The

Once the measurements are taken, a quadratic fit of the C-V

desired parameters, such as the trap densities, can be

data is related to the impurity density at a given depletion

extracted from the capacitance vs. frequency data. The

depth as follows for a p-type semiconductor:

measurements can be repeated at various temperatures.

≡

g(E,x

)dE

∫

2qεA

where:

N_DL = defect density (cm^-3)

C₁, C₀ = coefficients of quadratic fit of C-V data

q = electron charge (1.60 × 10^-19C)

ε = permittivity (F/cm)

A = area of solar cell (cm²)

ρe = charge density (C/cm³)

p = hole density (cm^-3)

x_e = distance from interface where E_F - E_v = E_e

Figure 14. C-f Sweep of Solar Cell

The coefficients C₀ and C₁ are determined via a full least-

squares best fit of the data to a quadratic equation:

Drive Level Capacitance Profiling (DLCP)

dQ/dV = C₂ (dV)² + C1*(dV) + C

Drive Level Capacitance Profiling (DLCP) is a technique for

However, only the C₀ and C₁ coefficients are used in the

determining the defect density (N_DL) as a function of depth

analysis.

of a photovoltaic cell¹. During the DLCP measurement,

the applied AC voltage (peak-to-peak) is swept and the DC

The Solar Cell DLCP or “dlcp” test allows making C-V

voltage is varied while the capacitance is measured. This

measurements for drive level capacitance profiling. During

is in contrast to the conventional C-V profiling technique,

these measurements, the total applied voltage remains

in which the AC rms voltage is fixed and the DC voltage

constant as the DC voltage bias is automatically adjusted

is swept.

as the AC voltage drive level amplitude varies. The AC

amplitude can be adjusted from 10 mVrms to 100 mVrms

In DLCP, the DC voltage is automatically adjusted to keep the

(14.14 mV to 141.4 mVp-p). The range of frequency can also

total applied voltage (AC + DC) constant while the AC voltage

be set from 1 kHz to 10 MHz. The capacitance is measured as

is swept. By maintaining a constant total bias, the exposed

the AC voltage is sweeping.

charge density (ρ_e) inside the material stays constant up to

a fixed location (x_e), which is defined as the distance from

the interface where E_F - E_v = E_e. This is also in contrast to

conventional C-V profiling, the analysis of which assumes

that the only charge density changes occur at the end of the

depletion region.¹

J. T. Heath, J. D. Cohen, W. N. Shafarman, “Bulk and metastable defects in CuIn1-xGaxSe2

thin films using drive-level capacitance profiling”, Journal of Applied Physics, vol. 95,

no. 3, p. 1000, 2004

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Solar Cells with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

Table 2 lists the input parameters used in the test, the

frequency (1 kHz to 10 MHz) or the temperature. To change

allowed range of input values, and descriptions. This

the temperature of the measurement, the user can add an

test was created from the DLCP User Library and the

Action to the project to control a temperature controller

ACSweep User Module. The user inputs the total applied

via the 4200A-SCS’s GPIB interface. The 4200A-SCS is

voltage (VmaxTotal), the AC start, stop, and step voltages

provided with user libraries for operating the Temptronics,

(VacppStart, VacppStop, and VacppStep), the time between

Lakeshore, and Triotek temperature controllers.

voltage steps (SweepDelay), the test frequency (Frequency),

the measurement speed (Speed), the measurement

range (CVRange), and offset compensation (OpenComp,

ShortComp, LoadComp, and LoadVal).

Table 2. Adjustable parameters for the dlcp test (ACSweep User Module)

Parameter

Range

Description

Applied DC Volts and ½ AC Volts

VmaxTotal

-10 to 10 volts

p-p

VacppStart

.01414 to .1414

Start Vac p-p

VacppStop

.02828 to .1414

Stop Vac p-p

VacppStep

.0007070 to .1414

Step Vac p-p

SweepDelay

0 to 100

Sweep delay time in seconds

Frequency

1E+3 to 10E+6

Test Frequency in Hertz

Speed

0, 1, 2

0=Fast, 1=Normal, 2=Quiet

Figure 15. Capacitance vs. AC voltage p-p of a solar cell

CVRange

0, 1E-6, 30E-6, 1E-3

0=autorange, 1 µA, 30 µA, 1 mA

Enables/disables open

OpenComp

1, 0

compensation for CVU

Pulsed I-V Measurements

Enables/disables short

Pulsed I-V measurements can be useful for studying

ShortComp

1, 0

compensation for CVU

parameters of solar cells. In particular, pulsed I-V

Enables/disables load

LoadComp

1, 0

measurements have been used to determine the conversion

compensation for CVU

efficiency, minimum carrier lifetime, and the effects of cell

LoadVal

1 to 1E+9

Load value

capacitance. The 4225-PMU, the 4200A-SCS’s optional

Ultra-Fast I-V Module, can output pulsed voltage and

Once the test is executed, the capacitance, AC voltage,

measure current, and can capture ultra-high-speed current

DC voltage, time stamp, frequency, and the defect density

or voltage waveforms in the time domain. In addition to

(N_DL) are determined and their values are listed in the Sheet.

sourcing a pulsed voltage, the PMU can sink current so it

The defect density is calculated in the Formulator using a

can measure a solar cell’s current output.

quadratic line fit of the C-V data. The coefficients (C₀ and

To make pulsed I-V measurements on a solar cell, the 4225-

C₁) of the quadratic equation are also listed in the Sheet.

PMU is connected to the cell as shown in Figure 16. Each

The user inputs the area and permittivity of the solar cell

PMU has two channels so the solar cell can be connected

to be tested into the Constants/Values/Units area of the

using either one or two channels. In the one-channel case

Formulator.

shown, one end of the cell is connected to the HI terminal of

Figure 15 shows the measurement results in the graph of

PMU CH1 and the other side of the cell is connected to the

capacitance vs. AC voltage p-p. Notice the coefficients

shield of the coax cable, which is the LO terminal of the PMU.

of the derived quadratic line fit and the defect density are

Unlike the DC I-V and C-V measurements, the 4225-PMU

displayed on the graph.

uses a two-wire technique. The Short Compensation

The capacitance measurements can be repeated at

feature can be used to “zero out” the voltage drops due to

various applied total voltages in order to vary the position

the cables so that a 4-wire measurement technique isn’t

of x_e. The energy (E_e) can be varied by changing the test

necessary.

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Electrical Characterization of Photovoltaic Materials and

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APPLICATION NOTE

Solar Cell

Connection to

SMA Coax

common terminal

Cable

50 Ω

CH1

CH2

4225-PMU

Figure 17. Pulsed I-V measurement on solar cell using 4225-PMU

Figure 16. Connecting the solar cell to the 4225-PMU Ultra-Fast I-V Module

Resistivity and Hall Voltage

Because solar cells are fairly capacitive, it is important to

ensure the pulse width is long enough for the pulsed I-V

Measurements

sweep. The waveform capture mode should be used to

Determining the resistivity of a solar cell material is a

verify the pulse width prior to generating the pulsed I-V

common electrical measurement given that the magnitude

sweep. The waveform capture mode enables a time-based

of the resistivity directly affects the cell’s performance.

current and/or voltage measurement that is typically the

Resistivity measurements of semiconductor materials

capture of a pulsed waveform. This can be used to perform

are usually performed using a four-terminal technique.

a dynamic test on the cell or used as a diagnostic tool for

Using four probes eliminates errors due to the probe

choosing the appropriate pulse settings in the pulsed I-V

resistance, spreading resistance under each probe, and

mode. Given that larger solar cells have larger capacitances,

the contact resistance between each metal contact and

it may be necessary to reduce the area of the cell itself to

the semiconductor material. Two common techniques for

avoid a long settling time in the measurement.

determining the resistivity of a solar cell material are the

four-point collinear probe method and the van der Pauw

The results of generating a pulsed I-V measurement sweep

method. The SolarCell project contains several tests for

on a silicon solar cell are shown in Figure 17. Note that the

making both types of measurements, which are described

current is in the fourth quadrant of the curve. This indicates

in the next few paragraphs.However, the Test Library also

that the PMU is sinking current; in other words, the current

contains individual tests for making both van der Pauw

is flowing out of the solar cell and into the PMU.

and Hall coefficient measurements. These tests can be

found by typing in the name of these tests in the search bar

in the Select view: vdp-surface-resistivity, vdp-volume-

resistsivity, or hall-coefficient. These tests are described

in the Keithley application note, “Making van der Pauw

Resistivity and Hall Voltage Measurements Using the

4200A-SCS Parameter Analyzer”.

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APPLICATION NOTE

k = a correction factor* based on the ratio of the probe

Four-Point Collinear Probe Measurement

spacing to wafer diameter and on the ratio of wafer

Method

thickness to probe spacing

The four-point collinear probe technique involves bringing

four equally spaced probes in contact with a material of

* The correction factors can be found in a standard four-

unknown resistance. The probe array is placed in the center

point probe resistivity test procedure such as Semi MF84:

of the material as shown in Figure 18. The two outer probes

Standard Test Method for Measuring Resistivity of Silicon

are used to source current and the two inner probes are

Wafers With an In-Line Four-Point Probe. This standard was

used to measure the resulting voltage difference across the

originally published by ASTM International as ASTM F 84.

surface of the material.

Using the Four-Point Probe Tests

The Solar Cell High Resistance or "hir" test or the Solar Cell

Current

Source

Low Resistance or "lor" tests are both used for making

four-point collinear probe measurements. The “hir” test can

be used for materials over a wide resistance range, ~1 mΩ

Voltmeter

to 1 TΩ. The 4200-PA preamps are required for making

high resistance measurements (>1MΩ). The “lor” test is

intended for measurements of lower resistance materials

(~1 mΩ-1 kΩ).

A screenshot of the “hir” test for measuring four-probe

resistivity is shown in Figure 19.

Figure 18. Four-point collinear probe resistivity configuration

The Solar Cell High Resistance test (hir) uses either three

From the sourced current and the measured voltage, the

or four SMUs to make the resistivity measurements. One

surface or sheet resistivity is calculated by:

SMU (SMU1) and the ground unit (GNDU) are used to source

current between the outer two probes. Two other SMUs

____

___

σ =

(SMU2 and SMU3) are used to measure the voltage drop

ln²

between the two inner probes. The Force HI terminal of

where:

each SMU is connected to each of the four probes. The SMU

σ = surface resistivity (Ω/■)

designation for this configuration is shown in Figure 20.

V = the measured voltage (V)

In the Formulator, the voltage difference between SMU2 and

= the source current (A)

SMU3 is calculated and the resistance and sheet resistivity

are derived from the voltage difference. The results appear

Note that the units for sheet resistivity are expressed as

in the Sheet in the Analyze pane of the test.

ohms per square (Ω/■) in order to distinguish this number

from the measured resistance (V/I), which is simply

When making high resistance measurements, potential

expressed in ohms. Correction factors to the resistivity

sources of error need to be considered in order to make

calculation may be required for extremely thin or thick

optimal measurements. Use a probe head that has a level of

samples or if the diameter of the sample is small relative to

insulation resistance between the probes that is sufficiently

the probe spacing.

higher than the resistance of the material to be measured.

This will help prevent errors due to leakage current through

If the thickness of the sample is known, the volume

the probe head. Ensure that the measurement circuit is

resistivity can be calculated as follows:

electrostatically shielded by enclosing the circuit in a metal

shield. The shield is connected to the LO terminal of the

____

___

ρ =

× t × k

ln²

4200A. The LO terminal is located on the GNDU or on the

outside shell of the triax connectors. Use triax cables to

where:

produce a guarded measurement circuit. This will prevent

ρ = volume resistivity (Ω-cm)

errors due to leakage current and significantly reduce the

t = the sample thickness (cm)

test time. Finally, the 4200-PA preamp option is required to

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APPLICATION NOTE

Figure 19. “hir” test module for measuring resistivity

Using the Formulator,

calculate the voltage

difference between

SMU2 and SMU3.

SMU1: Set to Current

SMU2: Set to Current

SMU3: Set to Current-

GNDU: Common

Bias (VMU) - Set

Bias (VMU) - Use as

connection for all

current level to

high impedance

SMUs. Or, this can be

haveabout a 10 mV

voltmeter, and set

SMU4 set to

drop between SMU2

current to 0 A on

Common.

and SMU3.

1 nA range.

Force HI

Figure 20. SMU designation for four-point collinear probe measurements

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Electrical Characterization of Photovoltaic Materials and

Solar Cells with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

source very small currents (nanoamp and picoamp range)

In the configuration shown in Figure 21, the Force HI

and to provide high input impedance (>1E16 ohms) to avoid

terminal SMU1 sources the current through Probe 1. The

loading errors when measuring the voltage difference.

voltage difference between Probes 2 and 3 is measured

through the Sense terminals of the two SMUs.

The Solar Cell Low Resistance (lor) test is only used for lower

resistance materials and requires only one or two SMUs. In

To compensate for thermoelectric offset voltages, two

this case, the Force and Sense terminals of the SMUs are

voltage measurements are made with currents of opposite

connected to the four-point probe as shown in Figure 20.

polarity. The two measurements are combined and

averaged to cancel the thermoelectric EMFs. The Solar Cell

Low Resistance (lor) test performs this offset correction

SMU1

SMU2 or GNDU

automatically by sourcing the two current values in the List

Sense HI

Sweep and then mathematically correcting for the offsets

in the Formulator. The corrected resistance and sheet

Force HI

resistivity are displayed in the Sheet.

Measuring Resistivity with the van der

Pauw Method

The van der Pauw (vdp) technique for measuring resistivity

uses four isolated contacts on the boundary of a flat,

arbitrarily shaped sample. The resistivity is derived from

eight measurements made around the sample as shown in

Figure 21. Connecting two SMUs for four-point probe measurements

Figure 22.

V₅

V₃

V₇

4 3

V₁

V₆

V₄

V₈

4 3

V₂

Figure 22. van der Pauw resistivity measurement conventions

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APPLICATION NOTE

Once all the voltage measurements have been taken, two

A plot of this function is shown in Figure 23. The value of “f”

values of resistivity, ρ_A and ρ_B, are derived as follows:

can be found from this plot once Q has been calculated.

(V₂ + V₄ - V₁ - V₃)

____

Once ρ_A and ρ_B are known, the average resistivity (ρ_AVG) can

ρA⁼

fAts__________________

ln²

be determined as follows:

ρA + ρB

AVG

(V₆ + V₈ - V₅ - V₇)

____

__________________

ρB⁼

f_Bt_s

ln²

1.0

where:

0.9

ρA and ρB are volume resistivities in ohm-cm;

t_s is the sample thickness in cm;

0.8

V₁-V₈ represent the voltages measured by the voltmeter;

I is the current through the sample in amperes;

0.7

fA and fB are geometrical factors based on sample

0.6

symmetry, and are related to the two resistance ratios Q_A

and Q_B as shown in the following equations (f_A = f_B = 1 for

0.5

perfect symmetry).

0.4

Q_A and Q_B are calculated using the measured voltages as

100

follows:

V₂ - V₁

_______

Q_A =

V₄ - V₃

Figure 23. Plot of f vs. Q

V₆ - V₅

_______

Q_B =

Using the vdp-resistivity subsite and

V₈ - V₇

vdp method tests

Also, Q and f are related as follows:

To automate the vdp resistivity measurements, the solarcell

Q - 1

e^0.693/f

_____

_______

project has a vdp-resistivity subsite with four tests: “i1-v23”,

arc cosh

Q + 1

0.693

)

“i2-v34”, “i3-v41”, and “i4-v12.” A screenshot of the test is

shown in Figure 24.

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APPLICATION NOTE

Figure 24. Screenshot of van der Pauw test

Test Name:

i2-v34

i4-v12

Common

Current Bias (+)

Common

Current Bias (-)

Voltmeter

SMU1

SMU2

SMU1

SMU2

SMU1

V12

SMU2

SMU1

V12

SMU2

SMU4

V34

SMU3

SMU4

V34

SMU3

SMU4

SMU3

SMU4

SMU3

Voltmeter

Current Bias (+)

Commo n

Current Bias (-)

Common

Test Name:

i3-v41

i1-v23

Voltmeter

Commo n

Voltmeter

Commo n

Current Bias (+)

Voltmeter

Current Bias (-)

Voltmeter

SMU1

SMU2

SMU1

SMU2

SMU1

SMU2

SMU1

SMU2

V41

V23

SMU4

SMU3

SMU4

SMU3

SMU4

SMU3

SMU4

SMU3

Voltmeter

Current Bias (+)

Voltmeter

Current Bias (-)

Commo n

Voltmeter

Common

Voltmeter

Figure 25. SMU configurations for van der Pauw measurements

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APPLICATION NOTE

Each terminal of the sample is connected to the Force

This settling time test can be generated by copying and then

HI terminal of an SMU, so a 4200A-SCS with four SMUs is

modifying one of the existing vdp tests. Switch the source

required. The four SMUs are configured differently in each

function from the sweep mode to the sampling mode.

of the four tests - one SMU supplies the test current, two

Then, in the Test Settings pane, take a few hundred or so

are configured as voltmeters, and one is set to common.

readings with a delay time of one second. Make sure that

This measurement setup is repeated around the sample,

the “Report Timestamps” box is selected. After the readings

with each of the four SMUs serving a different function in

are done, plot the voltage difference vs. time on the graph.

each of the four tests. A diagram of the function of each

The settling time is determined by observing the graph

SMU in each test is shown in Figure 25.

and finding the time when the reading is within the desired

percentage of the final value.

Adjusting the Test Parameters

Input the Thickness of the Sample: Enter the thickness of

Before executing the test, some of the test parameters

the sample into the Calc sheet at the subsite level. Select

must be adjusted based on the sample to be tested. In

the subsite vdp_resistivity. Go to the Subsite Data vdp-

particular, it’s necessary to specify the source current, the

device tab. It contains the output values of the voltage

settling time, and the thickness of the material.

differences and test current. From the Calc tab, the

thickness can be adjusted. The default thickness is 1 cm.

Input Source Current: Before running the project, input

the current source values based on the expected sample

Input Correction Factor: The resistivity formula found in

resistance. Adjust the current so that the voltage difference

the Calc sheet at the subsite level also allows inputting a

will not exceed approximately 25 mV to keep the sample in

correction factor, if necessary. The resistivity is multiplied

thermal equilibrium. In each of the four tests, enter both

by this number, which may be based on the geometry

polarities of the test current. The same magnitude must be

or uniformity of the sample. By default, the correction

used for each test.

factor is 1.

Input the Settling Time: For high resistance samples, it

Running the Project

will be necessary to determine the settling time of the

measurements. This can be accomplished by creating a test

The van der Pauw resistivity measurements must be run at

that sources current into two terminals of the samples and

the subsite level. Make sure that all four checkboxes to the

measures the voltage drop on the adjacent two terminals.

right of the vdp tests (“i1-v23,” “i2-v34,” “i3-v41,” and “i4-v12”)

The settling time can be determined by taking multiple

are selected and then select vdp_resistivity. Execute the

voltage readings and then graphing the voltage difference

project by using the Run button. Each time the test is run,

as a function of time.

the subsite data is updated. The voltage differences from

each of the four tests will appear in the Subsite Data vdp-

device Sheet tab. The resistivity will appear in the Subsite

Data Calc sheet as shown in Figure 26.

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APPLICATION NOTE

Figure 26. vdp resistivity calculation

With a positive magnetic field (B+), apply a current between

Hall Voltage Measurements

Terminals 1 and 3 of the sample, and measure the voltage

Hall effect measurements are important to semiconductor

drop (V_2-4+) between Terminals 2 and 4. Reverse the current

material characterization because the conductivity type,

and measure the voltage drop (V_4-2+). Next, apply current

carrier density, and Hall mobility can be derived from

between Terminals 2 and 4, and measure the voltage drop

the Hall voltage. With an applied magnetic field, the Hall

(V_1-3+) between Terminals 1 and 3. Reverse the current and

voltage can be measured using the configuration shown in

measure the voltage drop (V_3-1+) again.

Figure 27.

Reverse the magnetic field (B-) and repeat the procedure,

measuring the four voltages: (V_2-4-), (V_4-2-), (V_1-3-), and

B+

(V_3-1-). Table 3 summarizes the Hall voltage measurements.

Table 3. Summary of Hall Voltage Measurements

Current Forced

Voltage Measured

Voltage

Magnetic

Between

Designation

Flux

Terminals

V2-4+

B+

1-3

2-4

V4-2+

B+

3-1

4-2

V1-3+

B+

2-4

1-3

V3-1+

B+

4-2

3-1

V_2-4+

V2-4-

B-

1-3

2-4

V4-2-

B-

3-1

4-2

V1-3-

B-

2-4

1-3

Figure 27. Hall voltage measurement

V3-1-

B-

4-2

3-1

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APPLICATION NOTE

From the eight Hall voltage measurements, the average Hall

B+

coefficient can be calculated as follows:

Current Bias (+)

Voltmeter

Current Bias (-)

Voltmeter

t(V_4-2+ - V_2-4+ + V_2-4- - V_4-2-)

SMU1

SMU2

SMU1

SMU2

_____________________________

R_HC =

4BI

t(V_3-1+ - V_1-3+ + V_1-3- - V_3-1-)

R_HD =

_____________________________

4BI

SMU4

SMU3

SMU4

V34

SMU3

where:

Voltmeter

Common

Voltmeter

Common

R_HC and R_HD are Hall coefficients in cm³/C;

Voltage Measured: V_2-4+

Voltage Measured: V_4-2+

t is the sample thickness in cm;

B+

V represents the voltages measured in V;

Voltmeter

Current Bias (+)

Voltmeter

Current Bias (-)

SMU1

SMU2

SMU1

SMU2

I is the current through the sample in A;

B is the magnetic flux in Vs/cm²

V41

Once R_HC and R_HD have been calculated, the average Hall

coefficient (R_HAVG) can be determined as follows:

SMU4

SMU3

SMU4

SMU3

R_HC + R_HD

Common

Voltmeter

Common

Voltmeter

RHAVG =__________

Voltage Measured: V_1-3+

Voltage Measured: V_3-1+

From the resistivity (ρ_AVG) and the Hall coefficient (R_H), the

B-

Hall mobility (µ_H) can be calculated:

Current Bias (+)

Voltmeter

Current Bias (-)

Voltmeter

| R_H|

SMU1

V1 2

SMU2

SMU1

V1 2

SMU2

____

µ_H =

ρAVG

Using the 4200A-SCS to Measure the

SMU4

SMU3

SMU4

SMU3

Hall Voltage

Voltmeter

Common

Voltmeter

Common

The SolarCell project does not include a specific test

Voltage Measured: V_2-4-

Voltage Measured: V_4-2-

to measure the Hall voltage; however, four tests can be

added to the subsite for determining the Hall coefficient

B-

and mobility. Given that the configuration for the Hall

Voltmeter

Current Bias (+)

Voltmeter

Current Bias (-)

measurements is very similar to the van der Pauw

SMU1

SMU2

SMU1

SMU2

resistivity measurements, the vdp tests can be copied and

modified for making the Hall voltage measurements. The

modifications involve changing the functions of the SMUs.

Figure 28 illustrates how to configure the four SMUs in the

SMU4

SMU3

SMU4

SMU3

tests to measure the Hall voltage. Use the Output Value

Common

Voltmeter

Common

Voltmeter

checkboxes on the Test Settings pane of each test to return

Voltage Measured: V_1-3+

Voltage Measured: V_3-1-

the Hall voltages to the subsite-level Calc sheet.

A custom test must be added to control the magnet. For

Figure 28. SMU configurations for Hall voltage measurements

a GPIB-controlled electromagnet, users can write a user

module using KULT (the Keithley User Library Tool) to

control the magnitude and polarity of the electromagnet.

The code can be opened up in a custom test within the

project. Information on writing code using KULT is provided

in the 4200A-SCS Reference Manual.

136 | WWW.TEK.COM

Electrical Characterization of Photovoltaic Materials and

Solar Cells with the 4200A-SCS Parameter Analyzer

APPLICATION NOTE

If a permanent magnet is used, an Action from the Actions

Conclusion

Library can be used to create a dialog box Project Prompt

Measuring the electrical characteristics of a solar cell is

that will stop the test sequence in the project tree and

critical for determining the device’s output performance

instruct the user to change the polarity of the magnetic field

and efficiency. The 4200A-SCS simplifies cell testing

applied to the sample. A Project Prompt is a dialog window

by automating the I-V, C-V, pulsed I-V, and resistivity

that pauses the project test sequence and prompts the user

measurements and provides graphics and analysis

to perform some action. See the 4200A-SCS Reference

capability. For measurements of currents greater than 1 A,

Manual for a description of how to use Dialog Box Actions.

Keithley offers SourceMeter instruments that can be used

Finally, the Hall coefficient and mobility can be derived in

for solar cell testing. Information on these models and

the subsite-level Calc sheet. These math functions can be

further information on making solar cell measurements can

added to the other equations for determining resistivity.

be found on Keithley’s website: www.keithley.com.

Instead of using four separate tests and the subsite-level

Calc Sheet for making Hall voltage measurements, add the

hall-coefficient test from the Library, which combines all

the measurements and parameter extractions into one test.

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