DDR Electrical Verification and Memory System Debugging

May 22, 2012
Duration: 20:12
This webinar will explain how to prepare for performing electrical verification testing for DDR-based memory designs in accordance to the latest JEDEC specifications. Learn how to get signal access to memory chips, and execute electrical verification tests with a comprehensive toolset from Tektronix


Select Service


STAY INFORMED: Events & Seminars | Email Newsletter | Follow Tektronix on Twitter Follow Tektronix on Facebook Follow Tektronix on Google+ Follow Tektronix on Youtube

MEMBERSHIP: Create an account for exclusive membership privileges. Login