Electrical Validation and Debug

DDR Memory Interface

Electrical Validation

Electrical validation solutions allow you to capture, measure and characterize DDR memory interfaced signal behavior, jitter, eye size, crossover, strobes/clock alignment and bit errors confidently with the MSO/DPO70000 Series of oscilloscopes that provide high waveform capture rates combined with sophisticated tools like Pinpoint Triggering, Visual Triggering and Advanced Search and Mark capabilities.

Probing solutions for P7500 Tri-mode and P7300 differential high-bandwidth probes combined with a wide variety of interposers provide access to those hard to reach signals.

Our memory signal analysis package supports all popular memory standards such as DDR1/2/3/4, LPDDR1/2/3/4, GDDR3/5 and automatically identifies and performs gated measurements on the acquired data to provide a comprehensive report that includes pass/fail results.

Technologies
Memory Technology DDR DDR2 DDR2 DDR3 DDR3 DDR3L LPDDR3 LPDDR4 DDR4
Speed all rates Up to 400MT/s Up to 800MT/s Up to 1600MT/s Up to 2400MT/s Up to 1600MT/s Up to 1600MT/s Up to 4266MT/s Up to 3200MT/s
Max slew rate 5 5 5 10 12 12 8 18 18
Typical V swing 1.8 1.25 1.25 1 1 0.9 0.6 0.3 0.8
20-80 risetime (ps) 216 150 150 60 50 45 45 27 27
Equivalent Edge BW 1.9 2.7 2.7 6.7 8 8.9 8.9 15 15
Recommended Scope BW
(Max Performance)*
2.5 3.5 4 12.5 12.5 12.5 12.5 16 16
Recommended Scope BW
(Typ Performance)*
2.5 2.5 3.5 8 12.5 12.5 12.5 12.5 12.5
Oscilloscope Model MSO/DPO
70404C/D
MSO/DPO
70404C/D
MSO/DPO
70404C/D
MSO/DPO
70804C/D
MSO/DPO
71254C/D
MSO/DPO
71254C/D
MSO/DPO
71254C/D
MSO/DPO
71254C/D
MSO/DPO
71254C/D

 

  • Datasheet
    X
      • DDRA DDR-LP4 Memory Interface Electrical Verification and Debug Datasheet
      • Jitter and Eye-diagram analysis tools datasheet

 

Item

Description

MSO/DPO70000C/D The MSO/DPO70000C/D Series oscilloscopes deliver exceptional signal acquisition performance and analysis capability suitable for electrical verification and debug of the DDR memory interface. The digital channels on the MSO70000C/D models provide the ability to acquire and trigger on the events on the Address/Command bus.
P7500 Probes The P7500 high-bandwidth Tri-mode probes provide the ability to make accurate differential, single ended and common mode measurements with one probe setup.
P7300 Probes The P7300 probes are high-bandwidth, low circuit loading, low-noise differential probing solutions. They offer excellent signal fidelity for probing very fast clock speeds and edge rates.
Interposers A comprehensive set of interposer solutions for all major JEDEC Memory standards.
Opt. DDRA, Opt. LP-DDR4 Complete memory interface analysis package for DDR1/2/3/4, LPDDR1/2/3/4 and GDDR3/5. Option LP-DDR4 for LPDDR4 is available to use only on MSO/DPO70000 Series oscilloscopes.
Opt VET Capturing and finding the right characteristic of a complex event on the DDR memory interface can require hours of collecting and sorting through thousands of acquisitions for the event of interest. The optional Visual Trigger makes the identification of the desired waveform events quick and easy.
Opt DJA DPOJET is a comprehensive jitter and eye-diagram analysis tool, that simplifies discovering signal integrity and jitter related issues in high-speed serial, digital, and communication system designs.
Opt SDLA64 The SDLA Visualizer enables complete measurement circuit de-embed, simulation circuit embed and receiver equalization. The SDLA Visualizer with DPOJET jitter and eye analysis provide a comprehensive simulation and measurement environment for computer, communications and memory buses.
Title

Electrical Verification of DDR Memory

With the ever increasing DDR SDRAM Clock Frequencies and Signal Edge Rates, signal integrity and bus state verification techniques are increasingly important for DDR Memory design success. This application note focuses on techniques for triggering and decode of the command bus and isolating read/write signals, as well as on a variety of memory signal integrity measurements.

Triggering Fundamentals With Pinpoint® Triggering and Event Search & Mark for DPO7000

This document discusses some fundamentals of triggering, and how Pinpoint triggering takes triggering in real-time oscilloscopes to a new level.

P7500 Series Probes Tip Selection, Rework and Soldering Guide

How-to guide for P7500 Tip selection and soldering guide for use with Memory Component Interposers

Debugging Memory Interfaces using Visual Trigger on Tektronix Oscilloscopes

See how easy it is to capture events of interest using Visual Triggering, PinpointTriggering, and Advanced Search & Mark.

High-speed Interconnects: Characterization and Measurement-based Modeling

A primer that takes on the measurement issues of high-speed interconnects.

SDRAM Memory Systems: Embedded Test & Measurement Challenges

This DRAM memory primer provides an overview of DRAM concepts, presents potential future DRAM developments and offers an overview for memory design improvement through verification.

DDR Technology Fact Sheet

Tektronix provides a powerful and comprehensive test instrument portfolio for SDRAMs, memory controllers, advanced memory buffers, DIMMs, computer motherboards and embedded systems up to DDR3-1867 speeds and beyond.

Soldering a P7500 to a Nexus DDR Component Interposer

Step-by-step guide on soldering a P7500 probe to a Nexus DDR Component Interposer

Command & Protocol Verification of DDR+ DDR2+ and DDR3 SDRAM

Computer memories are not the only systems that continue to demand larger, faster, lower powered and physically smaller memories. Embedded systems applications have similar requirements. This application note highlights the power of the logic analyzer in verifying DDR2 SDRAM commands and protocols.

DDR2 & DDR3 - Proper Verification Approaches

Update on DDR2 & DDR3 Memory Bus Architecture along with JEDEC-recommended testing verification approaches.

Title

Electrical Validation: Oscilloscope Interposers

Selection guide of Oscilloscope Interposers for Electrical validation.

Title

Memory Interface Verification and Debug

This webinar will explain how to prepare for next generation DDR-based memory testing. Learn about the changes these new standards bring to electrical verification and how to prepare for proper signal access to LPDDR3 and DDR4 memory systems. Get advance knowledge to plan for proper instrument selection needed for performing electrical verification tests on these emerging standards.

DDR Electrical Verification and Memory System Debugging

Prepare for performing electrical verification testing for DDR-based memory designs in accordance to the latest JEDEC specifications.

 

Related Information

Memory Interface Verification and Debug Webinar

Memory Interface Verification and Debug WebinarLearn about next generation DDR-based memory testing in electrical validation for LPDDR3 and DDRA memory systems.

Electrical Verification of DDR Memory Application Note

Electrical Verification of DDR MemoryLearn triggering and decode techniques important for DDR Memory design success.

Get your Product Catalogs now!

Short form Tektronix product catalogs are available - Test and Measurement and Video Test.

Standards Bodies and partners

Select Service

X

STAY INFORMED: Events & Seminars | Email Newsletter | Follow Tektronix on Twitter Follow Tektronix on Facebook Follow Tektronix on Google+ Follow Tektronix on Youtube

MEMBERSHIP: Create an account for exclusive membership privileges.Login