Disassembly shows acquired data in the processor's instruction set mnemonics.
Symbolically identifies all processor bus cycles
Acquired data can be linked directly to HLL source files for source level debug
Up to 125 ps timing resolution enables detailed analysis of setup and hold times, edge-to-edge relationships, control timing, etc.
All data acquired by the logic analyzer is time stamped to enable accurate time correlation of code execution to other system busses or hardware activity.
Engineers can design a probe interface directly into the system under test. This allows the greatest control of probe loading and provides the most mechanically robust connection. Tektronix recommends designing the P6880 connectorless or P6434 probe connectors into prototype models. Third party breakout boards are also available, providing an alternative probing method.
Minimum System Requirements
TLA7xx mainframe and one TLA7X3 acquisition module, 102 channels, 100 MHz state, 32K deep (136 channels and up to 64M deep available)
Or TLA603 instrument, 102 channels, 100 MHz state, 32K deep (136 channels and up to 1M deep available)