Bit Error Rate Tester

Bridging the Information Gap

Each Tektronix Bit Error Rate Tester delivers unprecedented flexibility and performance to help compress your product development cycles and reduce verification testing costs. Quickly and confidently identify errors in digital bit streams with these highly advanced test and measurement instruments.

BERTScope® BSA Series Bit Error Rate Testers

A new approach to signal integrity measurements of serial data systems, combining the confidence of a BERT and the insight of an Oscilloscope.

BERTScope® CR Series Clock Recovery Instruments

The flexibility and accuracy you need for compliance measurements in conjunction with Bit Error Rate Testers and Sampling Oscilloscopes.

BERTScope® DPP Series Digital Pre-emphasis

Processor takes in single-ended inputs of data and clock and condition the signal by adding controllable amounts of pre-emphasis for use with a Bit Error Rate Tester.

BitAlyzer® BA Series Bit Error Rate Testers

Addressing signal integrity and BER issues faced by designers of sophisticated electronic and satellite communication system designs.

PPG3000 Series Programmable Pattern Generators

Capable of four simultaneous lanes of up to 32Gb/sec PRBS or custom digital pattern generation.

PED3000 Series Programmable Error Detectors

Provides up to 32 Gb/sec performance suitable for multi-channel, full rate error detection.

Title
BitAlyzer® 1500/1600 Bit Error Rate Tester Fact Sheet Key Specs and Ordering Information for the BitAlyzer 1500/1600 Bit Error Rate Tester
BERTScope Content Archive Request copies of historical content from SyntheSys Research (now Tektronix Inc.) related to BERTScope.
Anatomy of an Eye Diagram Description of an eye diagram, how it is constructed, and common method for generating one.
Characterizing an SFP+ Transceiver at the 16G Fibre Channel Rate Measurements needed to test an SFP+ transceiver to the 16G Fibre Channel standard.
Clock Recovery Primer+ Part 1 Look at clock recovery from a practical point of view, Part 1.
Clock Recovery Primer+ Part 2 Look at clock recovery from a practical point of view, Part 2.
Clock Recovery’s Impact on Test and Measurement This application note discusses the outside influences that can disturb the relationship between data and how it is clocked.
D.C. Blocks, a Trap for the Unwary When Using Long Patterns How important is it to focus on low end frequency specifications.
Dual-Dirac+ Scope Histograms and BERTScan Measurements Introduction to Dual-Dirac.
Exploring Power Supply Voltage Sensitivity in an IC with a BERTScope® Bit Error Rate Tester Using BER-based measurements with eye diagrams for problem resolution.

Title
Receiver Testing to Third Generation Standards Webinar With the advent of 3rd Generation Serial Standards at rates above 5 GT/sec, it is critically important to characterize receiver performance for a successful serial communication system design. This seminar, using PCI Express 3.0 and USB3 as example standards, will highlight the latest trends and illustrate important practical learnings for successful test execution.
How to Choose the Right Platform for Jitter Measurements Learn what to consider when selecting a platform for jitter measurements.
Beyond Receiver Interoperability Testing Webinar This 45 minute, live webinar will focus on the latest tools and techniques for properly performing jitter tolerance and stressed receiver sensitivity testing - including characterization and margin testing of next generation receivers. .