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BERTScope® Clock Recovery
Versatile Precision Clock Recovery and Analysis
The BERTScope Clock Recovery CR Series advanced architecture measures and displays the PLL frequency response from 100 kHz to 12 MHz; the highest loop bandwidth available for jitter testing on the market today. The first clock recovery instruments to allow full control of parameters including loop bandwidth, peaking/damping, and roll off.
Models in the BERTScope® Clock Recovery Series:
| Model | Description | Max Bit Rate | List Price | Shop Online or Get a Quote |
|---|---|---|---|---|
|
CR125A Read Reviews Write Review |
Clock Recovery Instrument | 12.5 Gb/s | $44,400 | Configure & Quote |
|
CR175A Read Reviews Write Review |
Clock Recovery Instrument | 17.5 Gb/s | $57,300 | Configure & Quote |
|
CR286A Read Reviews Write Review |
Clock Recovery Instrument | 28.6 Gb/s | $63,900 | Configure & Quote |
Features | Benefits |
| Data Rate Range up to 28.6 Gb/s | Continuous data rate coverage for next generation I/Os including PCIe 3.0, 10GBASE-KR, 16xFC, 25 & 28G CEI and 100GBASE-LR-4 & ER-4. |
| Independent control, measurement, and display of phase lock loop (PLL) BW, JTF (jitter transfer function) and peaking. | Provides accurate "Golden PLL" response for transmitter jitter compliance testing and stressed receiver sensitivity test calibration. Provides full flexibility for device characterization. |
| Clock Recovery Input Equalization | Enables clock recovery on high ISI signals without impacting the data stream under test. Recovered clock enables other analysis including "clean eye", application of FIR filtering to signal, and BER testing. |
| Edge Density Measurement | Allows instant determination of the mark density of the signal under test. |
| Jitter Spectral Analysis and Frequency Gated Integrated Jitter Measurements | Provides 200 Hz to 90 MHz display of jitter vs frequency with cursor based measurements of jitter peaks' amplitude and frequency. Frequency gated integrated jitter measurements PCIe 2.0 compliance testing. |
| Optional 24 MHz PLL BW | Meets the JTF bandwidth requirements of USB 3.0, 6 G SATA, and PCIe-Gen 3. |
| Extensive set of subrate (recovered) clock outputs. | Frequently needed for device reference clocks. |
| Title |
|---|
Clock Recovery Primer+ Part 1Look at clock recovery from a practical point of view, Part 1. |
Clock Recovery Primer+ Part 2Look at clock recovery from a practical point of view, Part 2. |
Clock Recovery’s Impact on Test and MeasurementThis application note discusses the outside influences that can disturb the relationship between data and how it is clocked. |
Dual-Dirac+ Scope Histograms and BERTScan MeasurementsIntroduction to Dual-Dirac. |
Stress Calibration for Jitter >1UIA practical methods for stress calibration. |
Stressed Eye PrimerIntroduction to stressed eye testing. |
BERTScope™ CR125A+ 175A+ & 286A Clock Recovery Fact SheetKey Specs and Ordering Information for BERTScope CR125A, 175A, & 286A Clock Recovery |
BERTScope® Clock Recovery Related Information
Get your FREE Eye Diagram and Clock Recovery Posters
These posters are about testing digital high speed communications electronics, and are intended for electronics engineers who work to verify compliance of their products.
Download Anatomy of an Eye Diagram App Note
Discusses different ways that information from an eye diagram can be sliced to gain more insight. It also discusses some basic ways that transmitters, channels, and receivers are tested.
Get your NEW Product Catalogs now!
Three short form Tektronix catalogs are available - Test and Measurement, Bench Products and Video Test.
Other Products to Consider
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