BERTScope® Clock Recovery

Versatile Precision Clock Recovery and Analysis

The BERTScope Clock Recovery CR Series advanced architecture measures and displays the PLL frequency response from 100 kHz to 12 MHz; the highest loop bandwidth available for jitter testing on the market today. The first clock recovery instruments to allow full control of parameters including loop bandwidth, peaking/damping, and roll off.

Models in the BERTScope® Clock Recovery Series: 

Model Description Max Bit Rate List Price Configure and Quote
CR125A Clock Recovery Instrument 12.5 Gb/s US$45,300 Configure & Quote
CR175A Clock Recovery Instrument 17.5 Gb/s US$58,400 Configure & Quote
CR286A Clock Recovery Instrument 28.6 Gb/s US$70,300 Configure & Quote



Data Rate Range up to 28.6 Gb/sContinuous data rate coverage for next generation I/Os including PCIe 3.0, 10GBASE-KR, 16xFC, 25 & 28G CEI and 100GBASE-LR-4 & ER-4.
Independent control, measurement, and display of phase lock loop (PLL) BW, JTF (jitter transfer function) and peaking.Provides accurate "Golden PLL" response for transmitter jitter compliance testing and stressed receiver sensitivity test calibration. Provides full flexibility for device characterization.
Clock Recovery Input EqualizationEnables clock recovery on high ISI signals without impacting the data stream under test. Recovered clock enables other analysis including "clean eye", application of FIR filtering to signal, and BER testing.
Edge Density MeasurementAllows instant determination of the mark density of the signal under test.
Jitter Spectral Analysis and Frequency Gated Integrated Jitter MeasurementsProvides 200 Hz to 90 MHz display of jitter vs frequency with cursor based measurements of jitter peaks' amplitude and frequency. Frequency gated integrated jitter measurements PCIe 2.0 compliance testing.
Optional 24 MHz PLL BWMeets the JTF bandwidth requirements of USB 3.0, 6 G SATA, and PCIe-Gen 3.
Extensive set of subrate (recovered) clock outputs.Frequently needed for device reference clocks.


Accessory Description
100PSRTFILTER 100 ps Rise Time Filter
BSARACK BSA-Rack Mount Kits
PMCABLE1M Precision Phase Matched Cable Pair, 1m

Clock Recovery’s Impact on Test and Measurement

This application note discusses the outside influences that can disturb the relationship between data and how it is clocked.

Dual-Dirac+ Scope Histograms and BERTScan Measurements

Introduction to Dual-Dirac.

Anatomy of an Eye Diagram

Description of an eye diagram, how it is constructed, and common method for generating one.

Six Sigma’ Mask Testing with a BERTScope® Bit Error Rate Tester

Using Six Sigma for citical insight.

Comparing Jitter Using a BERTScope® Bit Error Rate Testing

Comparison of DCD and F/2 Jitter.

Evaluating Stress Components using BER-Based Jitter Measurements

Self-verified jitter measurements using a BER-based Jitter Peak measurement.

Bridging the Gap Between BER and Eye Diagrams — A BER Contour Tutorial

Introduction to the BER Contour measurement.

BERTScope® Bit Error Rate Testers Jitter Map “Under the Hood”

A New Methodology for Jitter Separation

PCI Express® Transmitter PLL Testing — A Comparison of Methods

Overview of significant methods for performing PLL Testing

Stressed Eye: “Know What You’re Really Testing With”

Using BER-based analysis to improve stress calibration measurements.

BERTScope® Clock Recovery Related Information

Get your FREE Eye Diagram and Clock Recovery Posters

These posters are about testing digital high speed communications electronics, and are intended for electronics engineers who work to verify compliance of their products.

Download Anatomy of an Eye Diagram App Note

Discusses different ways that information from an eye diagram can be sliced to gain more insight. It also discusses some basic ways that transmitters, channels, and receivers are tested.

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