A fast-moving market requires faster Rx test processes and workflows. The BSX Series BERTScope is the quickest path to compliance. This new BERT receiver test solution has unique features that take the complexity out of receiver testing and brings confidence to Gen3/4 designs.
|Pattern generation and BER measurement from 1 Gb/s up to 32 Gb/s.||With no external mux/demux required for continuous operation up to the maximum rate, DUT handshaking is supported for a broad range of standards.|
|Integrated and calibrated impairments for stressed receiver testing.||Impairments including jitter and interference can be changed in real-time and can be controlled in multiple ways, including a front panel knob that allows the user to quickly change stress levels and identify receiver tolerance limits.|
|Link training support for PCI Express Gen3 and Gen4 and USB3.1 Gen1 and Gen2.||Fast equalization response to DUT requests enables link training compliance testing for PCIe Gen4 and beyond.|
|Optional built-in 4-tap Tx equalization for user controlled de-emphasis on pattern generator supplied data.||Supports pattern generator Tx equalization at data rates up to 32 Gb/s for coverage of a broad range of standards requirements.|
|Protocol-aware and bit-oriented pattern sequencer supporting up to 128 states and two levels of loop nesting.||Protocol-aware sequencing mode simplifies customer input to pattern memory without the need to apply protocol processing (scrambling, DC balancing, skip insertion) in the pattern editor. Transition between sequencer states can be made without regard to data stitching issues since the hardware maintains scrambling/DC balancing states.|
|Four, user programmable detector pattern matchers of up to 128 bits in length.||Protocol-based detector pattern match allows user to increment the pattern sequencer (or generate trigger signals) based upon messages received from the DUT, to create true stimulus/response test conditions.|
|Error location analysis including pattern sensitivity histogram.||The BSX Series offers the industry’s only sophisticated bit error analysis, to capture and store the context of each error (timing and bit location). A variety of error analysis tools give unprecedented visibility into the root cause of bit error rate problems. As an example, a pattern sensitivity histogram allows the user to correlate errors to specific bits in the test pattern.|
|Forward Error Correction (FEC) Emulation.||Error location information collected during BER testing allows the user to analyze bit error rates both before and after FEC to quickly identify the effectiveness of specific FEC implementations, and project corrected BER results from uncorrected BER measurements.|
|Integrated, BER-correlated eye diagram with measurement and analysis capability.||Enhances the debug experience unlike other BERTs by providing a quick look at the eye diagram of the incoming signal to assist the user in identifying the cause of synchronization issues. The ability to zoom and overlay BER results on the eye diagram in contour mode provides detailed insight into BER margins.|
|View Datasheet||BSA12500ISI||Differential ISI Board|
BSA-Rack Mount Kits
Overcoming Receiver Test Challenges in Gen4 I/O Applications
This new application note provides vital information on performing compliance and diagnostic tests for Gen4 enterprise receivers with Bit Error Rate Testers.
Understanding the Transition to Gen4 Enterprise & Datacenter I/O Standards
This whitepaper provides important information about adaptive equalization and link training, the impact of forward error correction (FEC) on compliance testing, debugging protocol handshaking and physical layer issues and new trends in channel performance evaluation along with other pertinent material when transitioning toGen4 standards.
Advanced Serdes Debug with a BERT
Learn simple strategies to pinpoint bit errors to the exact bit position and timing with powerful Error Location Analysis and a BERT.