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Высокоскоростная последовательная передача данных

Стандарты цифровых интерфейсов следующего поколения (последовательный, память, дисплей и т. д.) сдвигают пределы соответствия и инструментов отладки, представляя несколько конструкционных задач высокоскоростных приема и передачи, включая следующие.

  • Ограниченная доступность сигнала из-за небольших размеров устройств
  • Поведение шины с новыми схемами энергосбережения
  • Проверка новых возможностей кодировки и коррекции на сигнальных интерфейсах
  • Так много проверочных электрических испытаний и так мало времени!

Tektronix предлагает набор автоматических измерений, который сокращает циклы проверки физического уровня и обеспечивает их последовательность. В случае неудовлетворительных результатов проверки на соответствие цикл отладки можно сократить при помощи визуального запуска и декодирования протокола. При этом можно определять джиттер и шум от источников, таких как перекрёстные помехи или другие многоканальные шумы.

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Library

Title
MIPI Debug and Conformance Testing Challenges and Solutions
View the slides from the presentation, MIPI High Speed Serial Technologies: Debug & Conformance Testing Challenges and Solutions, created by Tektronix' Ramesh P.E, Principal Engineer and Parthasarathy …
Characterizing an SFP+ Transceiver at the 16G Fibre Channel Rate
Study the measurements needed to test an SFP+ transceiver to the 16G Fibre Channel standard, covering both Multi- Mode 850 nm and Single Mode 1310 nm interfaces. Included is a test and …
PCI Express® Transmitter PLL Testing — A Comparison of Methods
There are several methods of measuring PLL loop response, based on the type of test instrumentation used. As expected, the various methods trade off test accuracy, test speed (throughput), ease of …
PCIe Gen 5 Tx Tech Brief
Get an overview of PCI Express 5.0, testing, the challenges associated with that, and learn about the Tektronix PCIe 5.0 Transmitter Test Solution.
High Speed Interface Standards
This e-Guide will help you learn more about design challenges for testing PCIe 4.0, SAS, SuperSpeed USB, and DDR4 standards. Within the pages of the eGuide you will also get quick access to technical …
PCI Express Gen5 Automated Multi-Lane Testing
Comprehensive characterization of high-speed links such as PCI Express® require performing measurements of the Transmitter (Tx) and Receiver (Rx) across multiple differential lanes for the link under …
Fast+ Efficient Solutions for DVI Conformance Measurement Challenges
Tektronix provides all the DVI measurement solutions you need, ranging from high-bandwidth digital phosphor oscilloscopes (DPO) to probes to application-specific software. Tektronix has solved tough …
Remote Head Acquisition Improves High Speed Serial Measurement
As high speed serial data rates continue to increase, the need to maximize margin in measurements increases. Coaxial cables, even good quality ones can impact the measurement margin. Remote heads for …
Probing Tips for High Performance Design and Measurement
When a high performance system or component needs to be verified, it often requires attaching an oscilloscope probe. For high speed circuits, the effect of attaching a probe often cannot be ignored …
Title
PCIe Gen5 to Gen6 and Comparison to Electrical Ethernet
Watch as David Bouse explains the evolution of PCI Express from Gen5 to Gen6. Then hear from Pavel Zivny as he and David discuss PAM4 signaling in PCIe and how it compares with PAM4 as applied in …
How to Address Your Toughest Serial Bus Design Challenges with EDA and Measurement Correlation
This Tektronix webinar will teach engineers how to use modeling tools to correlate simulations with high-speed physical layer measurements on Serial Bus Standards using the DPO/MSO70000 Series …
DDR5 Test Challenges Webinar
Learn how you can address five of the thorniest measurement challenges associated with the new DDR5 standard. Get an update on the DDR5 Rx/Tx compliance test and insight in the latest characterization …
PCI Express Gen 4 and Gen 5 Transmitter and Receiver Validation
PCI Express I/O bandwidth has doubled every 3 years on average thereby leading to an increased demand for this full duplex high speed bus architecture. As the industry begins deploying the 5.0 …
MIPI C-PHY D-PHY Webinar
MIPI alliance standards have been driving the adoption of newer features and higher data rates for emerging mobile applications.  Oscilloscope-based protocol layer validation enables isolating …
Demystify MIPI D-PHY and C-PHY Transmitter and Receiver Physical Layer Test
During this webinar, you'll gain an understanding of MIPI test challenges for both MIPI high-speed physical layers. You'll also get useful tips and technical insights into characterizing and …
USB4 Webinar
View our USB4 Compliance and Characterization Test webinar to learn how you can address the measurement challenges associated with the new USB4 standard.
PCIe Gen6 PAM4 Signaling
Prepare for the next PCI Express inflection point by viewing this discussion of validation requirements for PCI Express Gen6.  We review newly introduced transmitter measurements including SNDR and …
PCI Express Gen 5 Reference Clock Webinar
This webinar presents an overview of reference clock jitter requirements as they have evolved and offers techniques for making these low femtosecond measurements using a real time oscilloscope. 
DDR5 Memory Characterization
While they promise to provide datacenters with large amounts of data at faster speeds and lower power consumption, DDR5 memory devices have unique test challenges.  Learn about characterization and …
PCI Express Gen 5 Update Webinar
Cloud-based computing power, storage capacity, and network bandwidth have led to the development of the PCI Express 5.0 specification for 32.0 GT/s. This webinar starts with an overview of 5.0 …