Data Pattern Generator

DG2040 • DG2030
The products on this datasheet are no longer being sold by Tektronix.

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Features & Benefits

  • Data Rate to 1.1 Gb/s Tests High-speed Logic Devices and Circuits
  • Data Pattern Depth to 256 K/channel Speeds Characterization
  • Multiple Output Channels Increases Flexibility
    • DG2040: 2
    • DG2030: 4 or 8
  • Control of Edge Timing (DG2040) Permits Jitter Simulation in Serial Data Streams
  • Precise Control of Output Parameters Include:
    • Variable Output Delay
    • Variable Output Level
    • Variable Rise and Fall Time Control (DG2030)
    • Tri-state Output Control (DG2030)
  • Fast Transition Times to 150 ps (DG2040) Aids Fast Logic Evaluation
  • Complementary Output (DG2040) Assures Excellent Signal Fidelity
  • Flexible Sequence Control with Jump, Event and Nested Loops
  • Large Display for Easy-to-Use Data Editing
  • Import Pattern Data with DG-link Software Utility
  • Integrate into ATE Systems via GPIB/RS-232-C Interface


  • Ultra Low Jitter for Clock Substitution
  • Characterize Device Timing for TTL, CMOS, ECL Families
  • Simulate Missing Functions in System or Subsystem Evaluation
  • Create Complex Data Patterns with Sophisticated Sequence, Looping, Jump on Event and Tri-state Output Control
  • Characterize and Verify ASIC, FPGA and DACs
  • Evaluate Media Storage Devices and Components (HDD, FDD, ODD, DVD)
  • Test Printer Engines or LCD Display Drivers
  • Construct Logic Verification Systems Utilizing Tektronix Oscilloscopes or Logic Scopes
  • Use in Conjunction with TLA Logic Analyzer to Provide Digital Stimulus

The DG2000 Series of pattern generators provide digital designers with the high performance tools needed to evaluate advanced digital semiconductors and logic circuits. Whatever you call your design process - characterization, debug, validation or verification - as a digital designer you must have a state-of-the-art digital pattern generation as you push the edge of the technology envelope and race to market.

Choose the best fit

The DG2000 Series is remarkable for its balanced approach to providing the appropriate class of instrument for a wide variety of digital design applications. Performance ranges from 1.1 Gb/s to 200 Mb/s and from 2 to 36 channels. The table illustrates the principal specifications for members of the DG2000 Series.




Data Rate

1.1 Gb/s

400 Mb/s

Pattern Depth

256 K/CH.

256 K/CH.

Rise & Fall Time (20% to 80%)

150 ps at 1Vp-p

1.5 ns at 2.5 Vp-p

No. of channels


4 or 8


Edge control

Variable tr & tf time

Critical Timing

The DG2000 Series is the ideal solution for applications where you must characterize device or circuit timing and amplitude margins. The DG2000 Series is perfect for simulating setup and hold violations or conditions of metastability. The DG2000 graphical user interface allows you to quickly create complex data patterns with a few keystrokes on the front panel. Use the advanced sequence editing capability of the DG2000 Series to insert infrequent faults or glitches in your data patterns to verify device or circuit recovery. The DG2000 Series is an invaluable tool, allowing you to simulate missing system functionality while meeting critical market windows. With the introduction of the DG2040, new capabilities are available to control clock and data jitter or modulate pulse edges on a selective basis (Figure 1).


Figure 1. The DG2040 allows specific edges to be identified and time adjusted or jittered by ±100 ps. An external modulation source can be used to provide continuously variable jitter.

Excellent Signal Flexibility

Each DG2040 complementary output generates data rates up to 1.1 Gb/s. The DG2040 defines high performance with <150 ps transition times, 10 ps delay timing resolution and programmable output levels of 250 mVp-p to 2.5 Vp-p (-1.125 mV to +3.5 V) in 5 mV steps. Pattern edges can be moved ±100 ps in 5 ps steps or modulated by an external source. SMA connectors are used for each complementary output channel and clock output. Figure 2 illustrates a number of adjustable signal parameters.

The DG2030 offers data rates up to 400 Mb/s on four or eight output channels with independently programmable timing delay with 20 ps resolution. Each channel provides variable output level of 250 mVp-p to 5 Vp-p (-1.5 V to +3.5 V) in 5 mV steps. Front panel BNC connectors are used for each channel.


Figure 2. Modify timing & pulse parameters such as level, delay and transition time.

Pattern Editing

The DG2000 Series is designed for serious digital designers who create their own digital patterns or rely on a logic simulator to supply digital vectors. A large graphical display simplifies data entry and editing functions, allowing the user to easily view and shape large segments of the data pattern (Figure 3). A wide variety of commonly used data patterns are built into the data editor to further simplify data creation. Built-in data functions include counters, shift registers, serial data converters and clocks.

Easy to use menu driven editing functions are provided to define data bit, cursor location and data width. Data can be manipulated at the bit, byte or word level. Various functions such as data cut/copy/paste, invert, magnify, insert and delete are supported, as are data shift, add and rotate. Advanced functions are used to create clock patterns and PRBS data. A variety of data presentations are available to clearly illustrate the data pattern including table, timing, binary and numeric.



Figure 3. Examples of data entry displays. Data is entered easily as hex data or diagrammatically.

Pattern Sequencing

All members of the DG2000 Series combine deep memory with advanced data flow sequencing to provide the designer with a flexible digital stimulus source.

Pattern sequencing is a capability that can extend the deep DG2000 Series pattern memory almost to infinity. Sequencing allows segments of pattern memory to be looped or repeated until some internal or external event occurs when pattern execution then continues. Each line in the sequence list can be controlled by an external event that can cause a jump to a different block of data. The DG2000 Series can have up to 4000 jumps at full clock rates. External event and inhibit Input signals are also used to control the flow and impedance of the DG2030 output.

Three types of sequences are offered:

  • Simple Sequence - For repeat, single or step operation modes
  • Enhanced Sequence - Supports more interactive and dedicated sequence control
  • Sub-Sequence - Supports defined sub-sequences that manage multiple blocks as a single block. Uses only one sequence entry in the sequence definition table

Figure 4. Flow chart illustrates sequence control flow.


Figure 5. Examples of editing menus showing automatic data pattern generation and editing tools.

Import Data

Tektronix' DG-Link software accessory imports data from Tektronix TDS oscilloscopes, TLS logic scopes or TLA logic analyzers for use as data pattern sources by the DG2000 Series. Logic simulators that output Comma Separated Value (CSV) format can also be used as a source file for DG-link and downloaded into the DG2000 Series.


Figure 6. DG-link software utility imports ASCII data vectors.


Output Data




Data Rate

0.1 b/s to 1100 Mb/s

0.1 b/s to 409.6 Mb/s

Sampling Rate

0.1 Hz to 1100 MHz

0.1 Hz to 409.6 MHz


7 digits

7 digits

Clock Output Period Jitter

<30 psp-p at 1100 MHz. Typical

<50 psp-p at 200 MHz. Typical

CH0 Period Jitter (Clock Pattern)

<20 psp-p at 1100 MHz. Typical

<200 psp-p at 400 MHz. Typical


PLL On, ±0.0001%

PLL On, ±0.0001%; PLL Off, ±3%

Pattern Depth

360 to 256 Kbits (4 increment)

90 to 256 Kbits (1 increment)

Data Width

2-Bits (complementary outputs) via front-panel SMA connectors

Standard: 4-Bits via front-panel BNC connectors.

Optional: 8-Bits via 4 front-panel, 4 rear-panel BNC connectors.


Maximum Number of Blocks - 256.

Maximum Number of Sequence Steps -

DG2040: 4000.

DG2030: 4000.

Block Repeats Per Line - 1 to 65536 or infinite.

Internal Trigger Generator

Range - 1.0 μs to 10.0 s.

Resolution - 3 digits, 0.1 μs minimum.

Accuracy - ±0.01%.

Data and Clock Output (DG2040)

Data -


Standard: CH 0 & CH 1 at front-panel SMA and Clock at rear panel SMA connectors.

VOH: -0.875 V to +3.5 V into 50 Ω.

VOL: -1.125 V to +3.25 V into 50 Ω.

Resolution: 5 mV.

Maximum Swing: 2.5 Vp-p into 50 Ω.

Minimum Swing: 250 mVp-p into 50 Ω.

DC Accuracy: ±3% of set value ± 50 mV.


Overshoot <5% at 1.5 Vp-p at 10 MHz.

Undershoot: <5% ±1.5 Vp-p at 10 MHz.

Impedance: 50 Ω.

Rise/Fall Time (20 to 80%): <150 ps at 1 Vp-p and 10 MHz.

Delay Function:

Delay channel: CH 0 or CH 1.

Delay time: -1 ns to +2 ns.

Delay resolution: 10 ps.

Accuracy: < (±3% of setting) ±|25 °C - Ta| * 15 ps ±100 ps (where Ta is the ambient temperature °C).

Channel Skew: (<±|25 °C - Ta|* 15 ps ±100 ps) where Ta is the ambient temperature °C.

Data and Clock Output (DG2030)

Data -


Standard: CH 0 to CH 3 and Clock at front-panel BNC connectors.

Optional: CH 4 to CH 7 at rear-panel BNC connectors.

VOH: -1.25 V to +3.5 V into 50 Ω.

VOL: -1.50 V to +3.25 V into 50 Ω.

Resolution: 5 mV.

Maximum Swing: 5 Vp-p.

Minimum Swing: 250 mVp-p.

DC Accuracy: (±3% of set value) ± 50 mV.

Aberrations: ≤5% at 3.5 Vp-p.

Impedance: 50 Ω.

Rise/Fall Time (20 to 80%): Variable at amplitude range from 2 Vp-p to 5 Vp-p.

Variable Range: 2.1 ns to 4.7 ns at 3.00 Vp-p - depends on amplitude setting.

Value in Fast: 0.25 Vp-p to 1 Vp-p; 500 ps.

1.7 ns at 3.00 Vp-p.

Accuracy: ±10% of setting ±500 ps.

Delay Function:

Delay channel: CH 0 to CH 7.

Delay time: -5 ns to 18 ns.

Delay resolution: 20 ps.

Accuracy: ±(3% of setting) ± |25 - Ta| × 60 ps ± 500ps (where Ta is the ambient temperature °C).

Channel Skew: <±300 ps (referenced to the clock output) at 10 MHz.

De-skew Range: ±1 ns.

Resolution: 10 ps.

Clock -

Amplitude: ±5% of setting ±50 mV at 1 MHz clock.

Aberration: ≤5% at 3.5 Vp-p.

Impedance: 50 Ω.

Rise/Fall Time (20 to 80%): Variable at amplitude range is 2 Vp-p to 5 Vp-p.

Variable Range: Depends on amplitude setting.

Value in Fast: 0.25 Vp-p to 1 Vp-p; 500 ps.

1.7 ns at 3.00 Vp-p.

Accuracy: ±10% of setting ±500 ps.

Auxiliary Inputs

Clock -

DG2040: Rear-panel BNC connectors (10 MHz reference).

DG2030: Rear-panel BNC connector.


DG2040: 10 MHz ± 0.1 MHz.

DG2030: DC to 409.6 MHz.

DG2040 -

Input voltage range: 0.2 V to 3.0 Vp-p.

Input voltage level: ±10 Vmax.

Impedance: 50 Ω, AC coupling.

DG2030 -

Impedance: 50 Ω, terminated to +0.5 V.

Delay to Clock Out: 36 ns (typical).

Trigger - Front-panel BNC connector.

Level: -5.0 V to +5.0 V.

Resolution: 0.1 V.

Threshold accuracy: ±(5% of setting) ±0.1 V.

Minimum Pulse Width: ≥10 ns.

Sensitivity: >0.5 Vp-p.

Impedance: 1 kΩ or 50 Ω.

Maximum Input: ±10 V into 1 kΩ, ±5 V into 50 Ω.

Polarity: Positive or negative.

Hold Off: 100 ns minimum.

Event - Rear-panel BNC connector.

Threshold Level: -5.0 V to +5.0 V.

Resolution: 0.1 V.

Set-up Time to Next Block:

DG2040: 230.5 to 254.5 clocks before the next block.

DG2030: 48 to 53 clocks before the next block.

Polarity: Positive edge.

Minimum Pulse Width: 100 ns.

Inhibit (DG2030 only) - Rear-panel BNC connector.


Off: Always enabled.

Internal: Controlled by CH 0 signal.

External: Controlled by inhibit input signal.

Both: Controlled by CH 0 or inhibit input signal.

Threshold Level: -5.0 V to +5.0 V into 1 kΩ.

Resolution: 0.1 V.

Delay to Data Output: 34 ns to 38 ns (typical).

Delay to Clock Output: 7 ns to 11 ns (typical).

Auxiliary Outputs

SYNC - Rear-panel BNC connector.


VOH, 2.5 V into 50 Ω 

VOL, 0 V into 50 Ω.

Pulse width:

DG2040: 32 to 36 clocks.

DG2030: 9 or 10 clocks.

Impedance: 50 Ω.

EVENT - Rear-panel BNC connector.

Level: Vhi, 2.5 V into 50 Ω; Vlo, 0 V into 50 Ω.

Output Term:

DG2040: 180 to 200 clocks.

DG2030: 45 to 50 clocks.

Delay Time:

DG2040: 194.5 to 214.5 clocks before data output change.

DG2030: 48 to 53 clocks before data output change.

Impedance: 50 Ω.

Programmable Interface -

GPIB: ANSI/IEEE 488.2-1987.

RS-232-C: 19.2 Kb/s, D-sub 9-Pin connector.

P3410 TTL Data Output Pod Characteristics
Data Output

Channels - 12.

Connector - 26-Pin header.

VOH - >4.4 V into 1 MΩ.

VOL - >0.1 V into 1 MΩ.

Rise/Fall Time - <5 ns into 1 MΩ, 10 pF (20% to 80%).

Internal Clock Out to Data Delay - 24 ns.

External Clock Input to Data Output Delay - 25 to 45 ns.

Trigger Input to Data Output Delay -

Internal Clock:

>6.25 MHz: 30 to 65 ns.

<6.25 MHz: 45 to 80 ns.

External Clock: 25 ns + 0.5 clock to 45 ns + 1.5 clock.

Delayed Channels

Delay Channel - CH 8, CH 9, CH 10, CH 11.

Delay Time - 0 to 20 ns.

Delay Resolution - 0.1 ns.

Channel Skew -

CH 0 and other channels, same pod: <3 ns.

CH 0 and CH 0, two pods of same type: <2 ns.

Event Input

Threshold Level - TTL.

Delay to Data Output - ≤50 ns + 50 clocks.

Set-up Time to Next Block - 47 to 54 clocks.

Inhibit Input

Level - TTL, 1 kΩ.

Delay to Data Output - 18 ns.

Internal Inhibit Delay - 5 ns.

Physical Characteristics



















*1 Including feet.

General Characteristics

Temperature -

Operating: +10 °C to +40 °C.

Nonoperating: -20 °C to +60 °C.

Humidity -

Operating: 20% to 80% (no condensation).

Nonoperating: 5% to 90% (no condensation).

Altitude -

Operating: Up to 4.5 km (15,000 ft.).

Nonoperating: Up to 15 km (50,000 ft.).

Vibration - Operating: 0.33 mm p-p, 10 to 55 Hz, 15 minutes.

Shock - Nonoperating: 294 m/s2 (30 g), half-sine, 11 ms duration.

Certification and Compliance

EC Declaration of Conformity - Meets intent of Directive 89/336/EEC for electromagnetic compatibility.

Safety - UL1244, CSA231, EN61010-1, IEC61010-1.


AC Line Power -

Voltage Ranges: 90 to 250 VAC.

Nominal Voltage: 100 V, 115 V, 200 V, 230 V, 240 V.

Line Frequency:

90 to 250 VAC: 48 to 63 Hz.

90 to 127 VAC: 48 to 440 Hz.

Power Consumption - 300 W maximum.

Maximum Current - 4 A.

Physical Characteristics

DG2000 Series Main Frame





















*1 Including feet.

*2 Including handle.

*3 Including front cover. 576 mm (22.2 in.) with handle extended.

Characteristics shown are typical. Please refer to individual product user manuals for complete specifications.


Last Modified: 2005-07-25 05:00:00

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