DDR

Tektronix' powerful and comprehensive test instrument portfolio for SDRAMs, memory controllers, DIMMs, computer motherboards and embedded systems will help you resolve design challenges quickly and efficiently.

 

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Electrical Verification of DDR Memory

With the ever increasing DDR SDRAM Clock Frequencies and Signal Edge Rates, signal integrity and bus state verification techniques are increasingly important for DDR Memory design success. This application note focuses on techniques for triggering and decode of the command bus and isolating read/write signals, as well as on a variety of memory signal integrity measurements.

Triggering Fundamentals With Pinpoint® Triggering and Event Search & Mark for DPO7000

This document discusses some fundamentals of triggering, and how Pinpoint triggering takes triggering in real-time oscilloscopes to a new level.

High-speed Interconnects: Characterization and Measurement-based Modeling

A primer that takes on the measurement issues of high-speed interconnects.

DDR Technology Fact Sheet

Tektronix provides a powerful and comprehensive test instrument portfolio for SDRAMs, memory controllers, advanced memory buffers, DIMMs, computer motherboards and embedded systems up to DDR3-1867 speeds and beyond.

Soldering a P7500 to a Nexus DDR Component Interposer

Step-by-step guide on soldering a P7500 probe to a Nexus DDR Component Interposer

SDRAM Memory Systems: Embedded Test & Measurement Challenges

This DRAM memory primer provides an overview of DRAM concepts, presents potential future DRAM developments and offers an overview for memory design improvement through verification.

Command & Protocol Verification of DDR+ DDR2+ and DDR3 SDRAM

Computer memories are not the only systems that continue to demand larger, faster, lower powered and physically smaller memories. Embedded systems applications have similar requirements. This application note highlights the power of the logic analyzer in verifying DDR2 SDRAM commands and protocols.

DDR2 & DDR3 - Proper Verification Approaches

Update on DDR2 & DDR3 Memory Bus Architecture along with JEDEC-recommended testing verification approaches.

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Memory Interface Verification and Debug

This webinar will explain how to prepare for next generation DDR-based memory testing. Learn about the changes these new standards bring to electrical verification and how to prepare for proper signal access to LPDDR3 and DDR4 memory systems. Get advance knowledge to plan for proper instrument selection needed for performing electrical verification tests on these emerging standards.

DDR Electrical Verification and Memory System Debugging

Prepare for performing electrical verification testing for DDR-based memory designs in accordance to the latest JEDEC specifications.

 

Memory Interface Verification and Debug

This webinar will explain how to prepare for next generation DDR-based memory testing. Learn about the changes these new standards bring to electrical verification and how to prepare for proper signal access to LPDDR3 and DDR4 memory systems.

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Download Anatomy of an Eye Diagram Application Note

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