Serial Data Link Analysis (SDLA)

Acceleration of signaling speeds and shrinking geometries create challenges for testing Computer, Communications and Memory busses. Serial Data Link Analysis tools allow you to de-embed the measurement circuit from the waveform providing a true representation of the signal. Channel models can then be embedded and receiver equalization applied to simulate what-if scenarios. Tektronix' advanced analysis solutions enable a seamless transition between characterization, compliance, and debug tasks required to bring your product to market.

• SDLA Visualizer for DSA/DPO/MSO70K Series Real Time Oscilloscopes: the SDLA Visualizer enables complete measurement circuit de-embed, simulation circuit embed and receiver equalization. The SDLA Visualizer with DPOJET Jitter and Eye Analysis provide a comprehensive simulation and measurement environment for Computer, Communications and Memory buses.

• 80SJNB Jitter, Timing, and Link Analysis for Sampling Oscilloscopes: When used with the Tektronix DSA8300 Sampling Oscilloscope, 80SJNB allows the user to specify a de-embed filter, Time Domain Waveform or S-Parameter for channel embedding and DFE/FFE Equalization. 80SJNB analysis software also performs timing and noise-based analysis to get a 3-D view of the eye diagram performance for deep, accurate evaluation on signals with speeds up to and beyond 50GHz.