Serial Data Webinars
As a leading participant in serial standards bodies, Tektronix solutions enable you to test with confidence against the latest and most challenging serial data requirements.
Learn about the latest technologies and their test requirements with these webinars.
- High Performance Mixed Signal Validation and Debug Webinar
Modern embedded and computing systems have become progressively more powerful by incorporating high-speed buses with mixed analog and digital subsystems. - Analyzing Long Records of Acquired Data Webinar
Jit Lim demonstrates how to use the DSA70000B Series performance ocsilloscopes to capture and analyze long records of information. Spread Spectrum Clocking (SSC), VCO Start-up Characterization and Power Supply Modulation Analysis. - Fundamentals of Signal Integrity Webinar
This 30-minute Webinar presented by Professor Geoff Lawday and Tektronix Marketing Manager David Ireland provide insight into signal integrity-related problems in digital and analog systems. This is an essential Webinar for Design Engineers working with complex digital systems and need clean, fast transitions free of transients. - SATA-IO Plugfest & Interop Workshop: Introduction to SATA 6Gb/s PHY Layer Testing
In this webinar you will learn techniques and tools to simplify the validation and debug progress for USB 3.0 PHY designs. You will also learn additional concepts needed to tackle the latest challenges in USB 3.0 transmitter, receiver and cable/channel testing. - The Case of the Closing Eye Webinar
The origins of digital problems often lie in the analog realm. See how signal integrity analysis can help you keep your eyes open. 15:56 min. Speaker: Ransom Stephens. - High Speed Serial Data Receiver Testing Webinar
This tutorial discusses the challenges in generating signals with increasing speeds for the latest serial standards and that thoroughly test any receiver with real world or "worst case" conditions. You will also learn how Direct Synthesis techniques enable a much more simplified method for many serial data test requirements. - How Stressing a Receiver Removes Stress from a Designer Webinar
Inducing the stress in your design can help you find it's hidden weaknesses. Learn the easy way to apply stress by understanding the hard way. - What the Dual Dirac Model Is and What It Is Not Webinar
In this tutorial, we'll cover the details of the dual-Dirac model, how and why it is used in specifications, how it is used to estimate the Total Jitter of a system, the assumptions it makes and where they fail. - Clock Recovery in Serial-Data Systems Webinar
- Acting on Impulse: Equalization and Emphasis Webinar
Learn how equalization can turn the tables on signal path effects. - The Meaning of Total Jitter Webinar
In this tutorial, we'll clarify the difference between peak-to-peak jitter and Total Jitter at a bit error ratio once and for all. We'll also discuss how TJ (BER) is estimated on oscilloscopes. - All About the Acronyms: RJ, DJ, DDJ, ISI, DCD, PJ, SJ Webinar
In this tutorial, we'll learn how to diagnose jitter problems by analyzing the different jitter components-each of which has its own acronym. We'll also see which of the components are independent and where they fit in specifications. - Jitter Analysis in Systems with Crosstalk Webinar
In this tutorial, we'll show why jitter and voltage noise should really be analyzed at the same time and how this type of analysis can be used to recognize processes that are not jitter, but can completely corrupt a jitter analysis, like crosstalk. - Reference Clock Jitter and Data Jitter Webinar
In this tutorial, we'll discuss the effect of clock jitter on serial data systems, the role it plays in both transmitters and receivers and how simple models can be used to isolate the clock jitter that impacts the bit error. - Advantages of Stress Testing Receivers with Synthesized Waveforms Webinar
Learn the best way to perform stress receiver tolerance tests with signal generation. By using an Arbitrary Waveform Generator, you gain the advantages of flexibility, ease of use, increased control, faster testing, and insightful diagnostics. - Simplifying Validation and Debug of USB 3.0 Designs Webinar
Universal Serial Bus has become known as the de facto standard for connecting personal computers and other peripheral devices. In this webinar you will learn techniques and tools to simplify the validation and debug progress for USB 3.0 PHY designs and the concepts needed to tackle the latest challenges in USB 3.0 transmitter, receiver and cable/channel testing.