Clarus™ SoC Post-Silicon Validation Solution

Accelerating Functional Verification of SoC Designs

Even with perfect design code (RTL), exhaustive validation is difficult and time consuming. The problem is amplified in ASIC and SoC (System-on-Chip) designs, where hardware, software, and firmware must come together at first silicon. Research shows that 75% of all devices fail to work first silicon comes back from the fab and the majority are due to functional escapes. When this occurs you need a post-silicon debug solution like Clarus.

When unexpected behaviors happen, design teams struggle with limited data to determine the root cause. They frequently spend hours, days, or even weeks, identifying the root cause of a problem. The result is delayed market entry for the product and reduced product profit from a missed market window.

Clarus enables thorough and rapid investigation and resolution of silicon errors in-system so you can minimize resolution cycle time and get to market quickly.

EE Times Article: Bridging software and hardware to accelerate SoC validation

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Clarus delivers fast validation and debugging of advanced SoC based systems. The solution fits seamlessly into your design process. The Implementor software makes employing on-chip capture simple. It allows design teams to quickly generate optimized on-chip infrastructure that works across multiple clock domains in minutes. Clarus works at the RTL level, it integrates seamlessly into any IC CAD flow.

The Clarus Infrastructure's highly configurable Any-Signal-Anytime architecture delivers real-time visibility into any number of internal signals you wish and makes the best possible use of on-chip resources and knowledge of your design RTL to minimize the area impact. Using less area than competing approaches, Clarus provides significantly greater visibility that can be easily adjusted to suit any die size budget.

Analyzer enables rapid validation by providing logic analyzer style views of the inner workings of the design and provides the power of advanced trigger conditions using RTL level naming so you can easily interpret the data.

The Clarus Embedded Instruments use advanced built-in compression techniques and conditional capture to obtain long traces of just the signals needed, synchronized to your trigger and aligned across all internal timing domains simultaneously. A scripting interface enables automation of captures over extended periods of time and provides the information you need to understand complex behavior that manifests over extended runtimes of your device.

A Unifying Instrumentation Solution

Implementor

The Implementor tool makes design for debug simple. The tool is used during the design phase to plan the debug infrastructure and automatically insert the infrastructure into the original RTL description of the design.

The OptiRank algorithm provides optimal signal capture recommendations. Using your RTL, the OptiRank algorithm analyzes, organizes, and ranks signals based upon interconnectedness, equivalency, your constraints, and your expert judgment. OptiRank will make recommendations for optimal signal capture coverage while leaving you in complete control.

In just a few clicks, the Implementor generates a specialized RTL-based hardware infrastructure based on your signal capture requirements and inserts it into your existing RTL for seamless integration with any CAD flow. The easy to use graphical user interface allows you to easily configure the capture memory size and observation network structure and gives instant feedback on gate cost.

The Implementor operates hierarchically on the RTL, so individual blocks or subsystems may be instrumented independently from each other and at the top level.

Analyzer

Debug quickly and thoroughly with logic analyzer-style views and advanced trigger conditions that use your RTL-level naming. Make use of built-in compression and conditional capture to obtain traces of over 1 millions clock cycles, time-correlated to your triggers and aligned across all internal timing domains simultaneously.

The easy-to-use graphical interface can save the capture configurations so you can repeat them later under different tests. For example, you can run the same test, but capture more data after the trigger while adding additional signals. The Analyzer makes it easy to extract anything you need, simply and easily.

Clarus™ SoC Post-Silicon Validation Solution

Accelerating Functional Verification of SoC Designs

A Unifying Instrumentation Solution

Implementor

Analyzer

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