Certus Whitepaper: Break Through Your ASIC Prototyping Bottlenecks
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Certus gives a single time-correlated simulator-style view across your ASIC design providing visibility into multiple FPGAs on a prototyping platform. The Analyzer allows rapid debug cycles and easy capture of signals through the JTAG interface. The Implementor allows designers to quickly implement debug visibility into each FPGA from a single interface.
Certus operates at any hierarchical level in the SoC or ASIC RTL design. The unique architecture allows observation of any number of signals on multiple FPGAs simultaneously, across any number of timing domains, aligned to the trigger condition. The Analyzer manages everything for you through a single JTAG or optional high performance embedded microprocessor interface.
Certus 2.0 allows designers to automatically instrument all of the signals likely to be needed in each of the FPGAs in a multi-FPGA ASIC prototype with a small FPGA LUT impact. This enables a proactive debug and instrumentation strategy, eliminating the need to re-compile the FPGA to debug each new behavior, typically a painful eight to eighteen hour ordeal with traditional tools. Today, when an engineer needs to recompile, it’s often a “Go-Home” event because the duration is so long they cannot do any other work.
Other key capabilities include:
Time-correlated capture results across clock domains and multiple FPGAs providing a system-wide view of the entire target design.
Certus fits seamlessly into any CAD flow. The easy-to-use Implementor software guides you through the process of signal selection and instrumentation, giving you instant feedback on logic requirements. Now, you don't have to wonder whether the design will still fit in your FPGA. The Analyzer quickly and easily captures signals so you can understand the internal functional performance of your design. A powerful command line interface lets you automate tests and make multiple capture runs, helping to resolve design problems that take extended periods of time to occur.
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The Implementor tool makes design for debug simple. The tool is used during the design phase to plan the debug infrastructure and automatically insert the infrastructure into the original RTL description of the design.
The OptiRank algorithm provides optimal signal capture recommendations. Using your RTL, the OptiRank algorithm analyzes, organizes, and ranks signals based upon interconnectedness, equivalency, your constraints, and your expert judgment. OptiRank will make recommendations for optimal signal capture coverage while leaving you in complete control.
In just a few clicks, the Implementor generates a specialized RTL-based hardware infrastructure based on your signal capture requirements and inserts it into your existing RTL for seamless integration with any CAD flow. The easy to use graphical user interface allows you to easily configure the capture memory size and observation network structure and gives instant feedback on gate cost.
The Implementor operates hierarchically on the RTL, so individual blocks or subsystems may be instrumented independently from each other and at the top level.
Debug quickly and thoroughly with logic analyzer-style views and advanced trigger conditions that use your RTL-level naming. Make use of built-in compression and conditional capture to obtain traces of over 1 millions clock cycles, time-correlated to your triggers and aligned across all internal timing domains simultaneously.
The easy-to-use graphical interface can save the capture configurations so you can repeat them later under different tests. For example, you can run the same test, but capture more data after the trigger while adding additional signals. The Analyzer makes it easy to extract anything you need, simply and easily.