Each of these solutions enable the validation of correct operation and the determination of the root cause of design issues faster in a unified and productive environment. This approach enables the user to control in-silicon instruments with a very high level of efficiency and automatically document the result.
A solution for SoC and ASIC prototypes that span multiple FPGA devices with the requirement to gain visibility across multiple devices for a prototype-wide view of the design behavior.
A solution for the SoC and ASIC designers who need efficient on-chip instrumentation and a methodology to insert those instruments minimizing die area while maximizing visibility.