Memory Interface Electrical Verification and Debug Datasheet

Features and Benefits

• Memory Validation and Debug: Comprehensive support for validation of multiple memory standards including DDR4 and LPDDR3
• Selectable Speed Grades: Support for JEDEC defined speed grades as well as custom speeds
• Auto Configuration Wizard: Easily set up the test configuration for performing electrical validation
• Qualified Multi-Rank Measurements: Measurements can be done on a selected rank of interest
• Cycle Type Identification: Navigate and timestamp all acquired read and write cycles
• Read & Write Burst Trigger Events: Quickly and easily isolate DQ, DQS and Clock signals using graphical based trigger systems
• De-embedding: Installed filters which de-embed interposer and probe effects to accurately represent the signal
• Flexible Test Selection: Select the Memory specification and the Speed Grade for targeted analysis
• Reporting: Automatically generate comprehensive reports that include pass/fail results
• Verification and Debug: Quickly switch between verification debug mode for deeper root cause analysis using DPOJET
• Probing Solutions: A wide range of probing solutions including solder tips, BGA interposers and MSO interposers
• Address/Command Bus Capture: The MSO5000 or MSO70000 Series Mixed Signal Oscilloscope can be used to precisely qualify timing of ADD/DMD bus cycles
• Programmable Interface: Allows development of remote client support for memory test

Applications

Validating the memory interface at the physical layer for signal integrity as well as timing to achieve the desired level of power / performance goals as well as for interoperability.

Option DDRA on the DSO/MSO5000, DPO7000 and DPO/DSA/MSO70000 series of Oscilloscopes provides support for multiple memory standards at JEDEC defined speed grades as well as custom speeds. The following Memory standards are supported by DDRA:

• DDR, DDR2, DDR3, DDR3L, DDR4
• LPDDR, LPDDR2, LPDDR3
• GDDR3, GDDR5

DDRA Configuration Wizard

The configuration wizard in DDRA provides a simple, step-by step and easy to use interface to speed up the test process. The user selects the memory technology of interest, speed grade, measurement group (Reads, Writes, Clocks, Address and Control Lines) and individual measurements within the group from the DDRA user interface.

Based on the user selections, DDRA automates oscilloscope scale settings, DQ and DQS levels and threshold and identifies different bus cycles using search and mark. The search and mark information is then used to separate out the Read and the Write cycles across the entire acquisition and qualify the measurement zones for use by advanced Jitter and Eye Analysis using DPOJET.

Additionally DDRA also allows the measurements be done only on the rank of interest in a multi-rank configuration by qualifying the bus cycles using the Chip Select Signal.

Comprehensive Measurements

Option DDRA adds a long list of JEDEC specific measurements for different memory standards to the already existing rich toolset of generic jitter, timing and signal quality measurements in DPOJET.

Results and reporting

Measurement configurations and JEDEC pass/fail limits are automatically applied for the selected measurements based on the memory specification and the speed grade selected. The results are included in statistics and plots to provide a complete analysis of the acquired waveform.

Hyperlinks within the report allow easy navigation between different sections in order to co-relate different measurement results.

DDRA reports

Verification versus debug

DDRA provides a comprehensive set of JEDEC measurements for different memory standards. In addition to this, it also provides access to the DPOJET advanced Jitter and Timing analysis engine that allows flexibility to reconfigure the existing measurements or to perform new measurements not defined by the JEDEC specification using new user specified test limits. Also features like logging, filters, histograms and time trends are available in DPOJET. This allows switching seamlessly between debug mode and verification mode.

Memory interface analysis in DPOJET

Oscilloscope triggering and waveform identification

Tektronix Pinpoint® trigger system provides the most comprehensive high performance trigger system in the Industry. The Pinpoint trigger system encompasses threshold and timing related triggers, Dual A- and B-Event Triggering, Logic Qualification, Window Triggering, and Reset Triggering.

The Advanced Search and Mark feature on the Tektronix MSO/DPO5000, DPO7000, and MSO/DPO/DSA70000 Series Oscilloscopes finds unique events in waveforms. It scans acquired waveform data for multiple occurrences of an event and marks each occurrence. Search and Mark features have a close relationship with the Pinpoint trigger system since they both can be used to discriminate signal characteristics. Search and Mark includes signal-shape discrimination features of the Pinpoint trigger system and extends them across live channels, stored data and math waveforms.

Pinpoint triggering

Visual Trigger makes the identification of the desired waveform events quick and easy by scanning through all acquired analog waveforms and graphically comparing them to geometric shapes on the display. By discarding acquired waveforms which do not meet the graphical definition, Visual Triggering extends the oscilloscope’s trigger capabilities beyond the traditional hardware trigger system.

Graphical triggering using Visual Trigger

These capabilities of the oscilloscope are very useful during the debug and are also extensively used by DDRA during the analysis.

Additional Capabilities using a Performance Mixed-Signal Oscilloscope

The Mixed Signal Oscilloscope allows probing more signals on the memory bus and to trigger on and view specific bus events. With a Tektronix MSO5000 or MSO70000 Series Oscilloscope, up to 16 digital channels can be used to view logic states of command and address signals such as RAS, CAS, WE, CE, CS, etc. On the MSO70000, signal integrity of these 16 inputs can be analyzed using the iCapture™ multiplexing feature, which allows any of the digital input signals to be internally routed to one of the scope’s four analog channels. Measurements involving command-bus cycle timing can also be analyzed using the bus-decode features of the MSO and DDRA software.

MSO70000 Series Oscilloscope probing command signals

Probing

In order to perform analysis on the memory bus, access to the signal plays a very important role. JEDEC specification requires that the signals be probed at the balls of the memory device which are difficult to access.

To overcome this problem Tektronix, in partnership with Nexus Technology, is offering a variety of probing options such as BGA interposers that support different memory devices in a variety of form factors. The interposers include an embedded tip resister placed very close to the BGA pad.

Introduction of an interposer and the oscilloscope probe may change the characteristics of the signal. De-embedding filters can be used to remove the effect of the interposer and the probe in the signal path to get an accurate representation of the signal at the probe point.

DDR4 Direct Attach Component Interposers (sizing relative to US coin)


P7500 Trimode Probeing System with accessories


LPDDR2 component package on package interposer

Logic debug and protocol analysis

When full protocol analysis or probing of the entire memory bus is required, a logic analyzer can provide this capability. The TLA7000 Series logic analyzers can also be linked with Tektronix oscilloscopes to provide an integrated test setup using tools such as iCapture mentioned above.

This eliminates the need for double probing and allows full analog capture of any signals probed by the logic analyzer. In addition, the iView™ display interface allows transfer of the oscilloscope data to the logic analyzer display, so that data from both instruments are analyzed and time-aligned on one display screen. Various types of probing solutions are available to support different form factors.

TLA Logic Analyzer and Probes for multi-channel signal capture

Oscilloscope bandwidth considerations for memory analysis

(Category) specifications

* Highest Accuracy on Faster Slew rates * Slew Rates are about 80% of the Max Spec * DDR3L, DDR4 and LPDDR3 is supported only on DSA/MSO/DPO70000C/D models only