Bit Error Rate Tester Datasheet

Characteristics

General

Characteristic	Description
Analog Bandwidth (Ch 1, Ch 2)	>10 GHz
Max Input Voltage (Ch 1, Ch 2, AUX)	3 Vp-p per channel
Insertion Loss (Ch 1, Ch 2)	3 dB
Impedance	50 Ω
Switching Speed	400 ns (typical)
Input/Output Connectors	SMA 3.5 mm female
Power Supply	Through USB connection to a control host (BERTScope Analyzer or Windows PC)
Software Control	Through USB connection to a control host
Inputs
Channel 1+	Single-ended / Differential (+) Internally AC-coupled
Channel 2+	Single-ended / Differential (+) Internally AC-coupled
AUX In	Internally converted to differential output Internally AC-coupled
Max Frequency	100 MHz
LFPS	Internal LFPS generator
Channel 1–	Differential (–) Internally AC-coupled
Channel 2–	Differential (–) Internally AC-coupled
Trigger In	CML
Nominal Voltage	V (Hi) 0 V V (Lo) –400 mV
Switch Control	3.3 V TTL
AUX Control	3.3 V TTL
Outputs
Output –	Differential (–)
Output +	Single-ended / Differential (+)
Trigger Out	3.3 V TTL (internally converted from CML Trigger In)

Pattern Generator*¹

Input/output specifications

Figure 1. Amplitude range.


Figure 2. Allowable combinations of termination and offset. Amplitude swings between 0.25 and 2.0 V allowed; should fit inside shaded area of graph. For example, SCFL uses a 0 V termination, and operates between approximately 0 and –0.9 V; as shown with dotted arrow, it falls within the operating range.

Clock outputs

Characteristic	Description
Frequency Range
BSA85C	0.1 to 8.5 GHz
BSA125C	0.1 to 12.5 GHz*2
BSA175C	0.5 to 17.5 GHz*2
BSA260C	1 to 26 GHz*2
BSA286C	1-28.6 GHz*2
Phase Noise	< –90 dBc/Hz at 10 kHz offset (typical)
Clock Output Divide Ratios	Option STR only

*¹ Rise times are measured 20% to 80% unless otherwise stated. Specifications are following a 20-minute warm-up period. Specifications subject to change.

*² Output at data rate ÷2 above 11.2 Gb/s.

 

Data outputs

Characteristic	Description
Date Rate Range
BSA85C	0.1 to 8.5 Gb/s
BSA125C	0.1 to 12.5 Gb/s
BSA175C	0.5 to 17.5 Gb/s
BSA260C	1 to 26 Gb/s
BSA286C	1 to 28.6 Gb/s
Format	NRZ
Polarity	Normal or Inverted
Variable Crossover	25 to 75%
Patterns
Hardware patterns	Industry-standard Pseudo-random (PRBS) of the following types: 2n – 1 where n = 7, 11, 15, 20, 23, 31
RAM patterns
BSA85C       BSA125C       BSA175C       BSA260C       BSA286C	128 bits to 128 Mb total, allocated in 32 Mb portions to each of two A/B pages. Single page max is 128 Mb
Library	Wide variety including SONET/SDH, Fibre Channel based such as k28.5, CJTPAT; 2n patterns where n = 3, 4, 5, 6, 7, 9; Mark Density patterns for 2n where n = 7, 9, 23; and many more
Error Insertion
Length	1, 2, 4, 8, 16, 32, 64 bit bursts
Frequency	Single or repetitive

 

Data, clock amplitudes, and offsets

Characteristic	Description
Configuration	Differential outputs, each side of pair individually settable for termination, amplitude, offset
Interface	DC coupled, 50 Ω reverse terminated, APC-3.5 connector. Calibration into 75 Ω selectable, other impedances by keypad entry. User-replaceable Planar Crown® adapter allows change to other connector types
Preset Logic Families	LVPECL, LVDS, LVTTL, CML, ECL, SCFL
Terminations	Variable, –2 to +2 V Presets: +1.5, +1.3, +1, 0, –2 V, AC coupled
Allowable Amplitudes, Terminations, and Offsets	See Figures 1 and 2

 

Data, clock waveform performance

Model	Rise Time	Jitter
BSA85C	25 ps max, 23 ps typical (10-90%)   1 V amplitude, at 8.0 Gb/s	<10 ps p-p (typical, for data rates ≥1 Gb/s) <0.025 UI (typical, for data rates <1 Gb/s)
BSA125C
BSA175C
BSA260C		8 ps p-p (typical at 25.78 Gb/s data rate)
BSA286C		<4 ps p-p Data Dependent Jitter (@ 14.05 Gb/s, @16.0 Gb/s, @25.781 Gb/s, @28.05 Gb/s) <300 fs RMS Random Jitter (@28.05 Gb/s, @25.781 Gb/s, @25.0 Gb/s) <400 fs RMS Random Jitter (@14.025 Gb/s, @16.0 Gb/s) <550 fs RMS Random Jitter (@12.0 Gb/s) 1 V amplitude at designated frequencies.

 

Clock/data delay

Characteristic	Description
Range	(Greater than 1 bit period in all cases)
Up to 1.1 GHz	30 ns
Above 1.1 GHz	3 ns
Resolution	100 fs
Self Calibration	At time of measurement, when temperature or bit rate are changed, instrument will recommend a self calibration. Operation takes less than 10 seconds

 

Pattern Generator ancillary connections

Front-panel Pattern Generator connections

External clock input

Characteristic	Description
Allows use of an external clock source to clock the BERTScope. Models equipped with stress are able to add impairments to incoming clock, including when external signal has Spread Spectrum Clocking (SSC) in excess of 5000 ppm imposed on it.
Frequency Range
BSA85C	0.1 to 8.5 GHz
BSA125C	0.1 to 12.5 GHz
BSA175C	0.5 to 17.5 GHz
BSA260C	1 to 26 GHz
BSA286C	1 to 26 GHz
Nominal Power	900 mVp-p (+3 dBm)
Maximum Power	2.0 Vp-p (+10 dBm)
Return Loss	Better than –6 dB
Interface	50 Ω SMA female, DC coupled into selectable termination voltage

HF Jitter (Option STR only)

Characteristic	Description
One of two jitter insertion inputs. Can be used to insert SJ, RJ, BUJ if desired.
Frequency Range	DC to 1.0 GHz
Jitter Amplitude Range	Up to 0.5 UI max
Input Voltage Range	0-2 Vp-p (+10 dBm) for normal operation 6.3 Vp-p (+20 dBm) max nondestructive input
Data Rate Range	Supports data rate ranges from 1.5 to 8.5 Gb/s (BSA85C), 12.5 Gb/s (BSA125C), 17.5 Gb/s (BSA175C), 22.4 Gb/s (BSA260C, BSA286C), with limited performance to 622 Mb/s (BSA260C/BSA286C excluded)
Interface	SMA female, 50 Ω, DC coupled into 0 V

Sub-rate clock output

Characteristic	Description
BERTScope standard models have clock divided by 4. BERTScope Option STR models have additional capabilities.
Frequency Range		With Option STR
BSA125	0.025 to 2.125 GHz	8.5 GHz
	0.025 to 2.8 GHz	11.2 GHz
BSA175	0.125 to 2.8 GHz	11.2 GHz
BSA260	0.250 to 3.25 GHz	13 GHz
BSA286	0.250 to 3.575 GHz	14.3 GHz
Amplitude Range	0.6 Vp-p, nominal, centered around 0 V
Transition Time	<500 ps
Interface	SMA female, 50 Ω, DC coupled into 0 V

Trigger output

Characteristic	Description
Provides a pulse trigger to external test equipment. It has two modes: 1. Divided Clock Mode: Pulses at 1/256th of the clock rate 2. Pattern Mode: Pulse at a programmable position in the pattern (PRBS), or fixed location (RAM patterns) Stress modulation added on models so equipped, when enabled.
Minimum Pulse Width	128 Clock Periods (Mode 1) 512 Clock Periods (Mode 2)
Transition Time	<500 ps
Jitter (p-p, data to trigger)	<10 ps, typical (BSA175C, BSA260C, BSA286C)
Output Levels	>300 mVp-p, center at 650 mV
Interface	50 Ω SMA female

 

Rear-panel Pattern Generator connections

Pattern Start Input

Characteristic	Description
For users wanting to synchronize patterns of multiple data streams from multiple instruments simultaneously.
Logic Levels	LVTTL (<0.5 V Low, >2.5 V High)
Threshold	+1.2 V typical
Max Nondistructible Input Range	–0.5 V to +5.0 V
Minimum Pulse Width	128 serial clock periods
Maximum Repetition Rate	512 serial clock periods
Interface	SMA female, >1 kΩ impedance into 0 V

 

Page select input

Characteristic	Description
In A-B Page Select mode, allows external control of pattern. Software control over rising or falling edge trigger, continuous Pattern B after completion of Pattern A, or run B only once before reverting back to A.
Logic Levels	LVTTL (<0.5 V Low, >2.5 V High)
Threshold	+1.2 V typical
Max Nondistructible Input Range	–0.5 V to +5.0 V
Minimum Pulse Width	1 pattern length
Interface	SMA female, >1 kΩ impedance into 0 V

 

Sinusoidal interference output (Option STR only)

Characteristic	Description
SI output from internal generator. Can be used to apply SI after external ISI channel.
Frequency Range	0.1-2.5 GHz
Output Voltage	0-3 Vp-p
Interface	0-3 Vp-p

 

Low-frequency jitter input (Option STR only)

Characteristic	Description
Allows use of external low-frequency jitter source to modulate the stressed Pattern Generator output.
Frequency Range	DC to 100 MHz
Jitter Amplitude Range	Up to 1.1 ns, can be combined with other internal low-frequency modulation
Input Voltage Range	0-2 Vp-p (+10 dBm) for normal operation 6.3 Vp-p (+20 dBm) max nondestructive input
Data Rate Range	Up to 8.5 Gb/s (BSA85C), 12.5 Gb/s (BSA125C), 17.5 Gb/s (BSA175C), 22 Gb/s (BSA260C), and 28.6 GB/s (BSA286C)
Interface	SMA female 50 Ω, DC coupled into 0 V

 

Low-frequency sinusoidal jitter output(Option STR Only)

Characteristic	Description
To allow phasing of two BERTScopes together, in-phase or anti-phase.
Frequency	As set for internal SJ from GUI
Amplitude	2 Vp-p, centered at 0 V
Interface	SMA female

 

Reference input

Characteristic	Description
To lock the BERTScope to an external frequency reference from of another piece of equipment.
Frequency	10, 100, 106.25, 133.33, 156.25, 166.67, or 200 MHz
Amplitude	0.325 to 1.25 Vp-p (–6 to +6 dBm)
Interface	50 Ω SMA female, AC coupled

 

Reference output

Characteristic	Description
Provides a frequency reference for other instruments to lock to.
Configuration	Single Ended (Ref-Out not used) (BSA125C) Differential
Frequency	10, 100, 106.25, 133.33, 156.25, 166.67, or 200 MHz
Amplitude	1 Vp-p (+4 dBm) nominal, each output, (2 Vp-p differential)
Interface	50 Ω SMA female, AC coupled

 

Clock path details

BSA85C

Functional block diagram of the clock path for models with stress capability, BSA85C.


Available divide ratios from clock-related output, by bit rate, using the internal clock, BSA85C***.

BSA125C, BSA175C, BSA260C, and BSA286C

Functional block diagram of the clock path for models with stress capability, BSA85C, BSA125C, BSA175C, BSA260C, BSA286C.

* This output can also provide a full-rate jittered clock.

** Stress may be added to an external clock on appropriate models. Stress operating range is from 1.5 to 11.2 Gb/s. External clock must have a duty cycle of 50% ±2%.

*** All listed ratios available for an external clock input over entire bit rate range, limitations for internal clock only. Minimum specified frequency of the clock output is 100 MHz. Operation below this rate will be uncalibrated.

 

The BSA125, BSA175, BSA260, and BSA286C models use an internal Double Data Rate (DDR) architecture to operate at data rates ≥11.2 Gb/s. When operating at 11.2 Gb/s or higher data rate, the clock output will be 1/2 the data rate.

External clock can be specified to be either full or half data rate. When full rate is selected, the Pattern Generator will operate in DDR mode when the input clock frequency is 11.2 GHz or higher.

These ratios apply to operation from internal clock only. External clock will be output at 1/2 rate when half rate is selected, or when full rate is selected and clock rate is ≥11.2 GHz.

The minimum data rate specified for the main clock output is 500 Mb/s. Output will be uncalibrated when operated at divided rates lower than 500 Mb/s.

Multi-rate and sub-rate divider ratios for main clock output (BSA125C, BSA175C, BSA260C, BSA286C)

Data Rate (Gb/s)	Ratios for Main Clock Out	Ratios for Sub-rate Clock Out*3
500-750 Mb/s	1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, 20, 24, 32, 36	1, 2, 4
0.75-1.5 Gb/s	1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, 20, 24, 25, 28, 30, 32, 35, 36, 40, 42, 45, 48, 54, 56, 64, 72, 81	1, 2, 4, 8
1.5-3 Gb/s	1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, 20, 24, 30, 32, 32, 35, 36, 36, 40, 42, 45, 48, 50, 54, 56, 60, 64, 70, 72, 80, 81, 84, 90, 98, 108, 112, 126, 128, 144, 162	1, 2, 4, 8, 16
3-6 Gb/s	1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, 20, 24, 30, 32, 32, 35, 36, 36, 40, 42, 45, 48, 50, 54, 56, 60, 64, 70, 72, 80, 81, 84, 90, 98, 100, 108, 112, 120, 126, 128, 140, 144, 160, 162, 168, 180, 192, 196, 216, 224, 252, 256, 288, 324	1, 2, 4, 8, 16, 32
6-11.2 Gb/s	1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, 20, 24, 30, 32, 32, 35, 36, 36, 40, 42, 45, 48, 50, 54, 56, 60, 64, 70, 72, 80, 81, 84, 90, 98, 108, 112, 126, 128, 140, 144, 144, 160, 162, 162, 168, 180, 192, 196, 200, 216, 224, 240, 252, 256, 280, 288, 320, 324, 360, 384, 392, 432, 448, 504, 512, 576, 648	1, 2, 4, 8, 16, 32, 64
11.2-12 Gb/s	2, 4, 8, 10, 12, 14, 16, 18, 20, 24, 28, 32, 36, 40, 48, 60, 64, 64, 70, 72, 72, 80, 84, 90, 96, 100, 108, 112, 120, 128, 140, 144, 160, 162, 168, 180, 196, 200, 216, 224, 240, 252, 256, 280, 288, 320, 324, 336, 360, 384, 392, 432, 448, 504, 512, 576, 648	2, 4, 8, 16, 32, 64
12-26 Gb/s	2, 4, 8, 10, 12, 14, 16, 18, 20, 24, 28, 32, 36, 40, 48, 60, 64, 64, 70, 72, 72, 80, 84, 90, 96, 100, 108, 112, 120, 128, 140, 144, 160, 162, 168, 180, 196, 216, 224, 252, 256, 280, 288, 288, 320, 324, 324, 336, 360, 384, 392, 400, 432, 448, 480, 504, 512, 560, 576, 640, 648, 720, 768, 784, 864, 896, 1008, 1024, 1152, 1296	2, 4, 8, 16, 32, 64, 128

*³ Sub-rate clock connector can also output a full-rate stressed clock up to 11.2 Gb/s, or half-rate stressed clock at rates ≥11.2 Gb/s.

Pattern Generator stressed eye

• Flexible, integrated stressed eye impairment addition to the internal or an external clock
• Easy setup, with complexity hidden from the user with no loss of flexibility
• Verify compliance to multiple standards using the BERTScope and external ISI filters. Standards such as:
• OIF CEI
• 6 Gb SATA
• PCI Express^®
• XFI
• USB 3.0
• SONET
• SAS 2
• XAUI
• 10 and 100 Gb Ethernet
• DisplayPort
• Sinusoidal interference may be inserted in-phase or in anti-phase, or sent externally to be summed after an external ISI reference channel
• Sinusoidal jitter may be locked between two BERTScopes in-phase or anti-phase, as required by OIF CEI

Flexible external jitter interfaces

• Front Panel External High Frequency Jitter Input Connector – Jitter from DC to 1.0 GHz up to 0.5 UI (max) may be added, of any type that keeps within amplitude and frequency boundaries
• Rear Panel External SJ Low Frequency Jitter Input Connector – Jitter from DC to 100 MHz up to 1 ns (max) may be added
• Rear Panel SJ Output
• Sinusoidal Interference Output Rear Panel Connector

Note: Internal RJ, BUJ, and external high-frequency jitter input limited to 0.5 UI, combined, further limited to 0.25 UI each when both are enabled. Rear-panel low-frequency jitter input can be used to impose additional jitter; sum of external low-frequency jitter, internal low-frequency SJ to 10 MHz, PCIe LFRJ and PCIe LFSJ (with Option XS) is limited to 1.1 ns. This limit does not apply to Phase Modulation (PM) from Option XSSC.

Amplitude and ISI impairments

ISI

Add externally: For example, long coax cable length, or Bessel-Thompson 4th Order Filter with –3 dB point at 0.75 of bit rate, etc.

For applications requiring circuit board dispersion, the BSA12500ISI differential ISI accessory board may be used.

Sinusoidal interference

• Supports full data rate range of BERTScope
• 100 MHz to 2.5 GHz
• Adjustable in 100 kHz steps
• Adjustable from 0 to 400 mV
• Common mode or differential
• Available from rear-panel 50 Ω SMA connector, single ended with data amplitude from 0 to 3 V adjustable from GUI, same frequency range and step size as internal adjustment

Jitter impairments

Bounded uncorrelated jitter

• Supports data rates from 1.5 to 8.5 Gb/s (BSA85C), to 12.5 Gb/s (BSA125C), 17.5 Gb/s (BSA175C), 22.4 Gb/s (BSA260C), and 22 Gb/s (BSA286C) with limited performance to 622 Mb/s (BSA260C/BSA286C excluded)
• Internal PRBS-7 Generator
• Variable up to 0.5 UI
• 100 Mb/s to 2.0 Gb/s
• Band-limited by selected filters (see table below)

BUJ rate	Filter
100 to 499	25 MHz
500 to 999	50 MHz
1,000 to 1,999	100 MHz
2,000	200 MHz

 

Random jitter

• Supports data rates from 1.5 to 8.5 Gb/s (BSA85C), to 12.5 Gb/s (BSA125C), 17.5 Gb/s (BSA175C), 22.4 Gb/s (BSA260C), and 22 Gb/s (BSA286C) with limited performance to 622 Mb/s (BSA260C/BSA286C excluded)
• Variable up to 0.5 UI
• Band-limited 10 MHz to 1 GHz
• Crest factor of 16 (Gaussian to at least 8 standard deviation or ~1×10^–16 probability)

Sinusoidal jitter

Data rate	Internal SJ frequency	Maximum internal SJ amplitude
Up to 8.5 (BSA85C), 12.5 (BSA125C), 17.5 (BSA175C), or 22.4 (BSA260C)	1 kHz to 10 MHz*4	1100 ps
	10 MHz to 100 MHz	200 ps
22.4-26 Gb/s (BSA260C) or 28.6 Gb/s (BSA286C)	1 kHz to 100 MHz	84 ps

*⁴ Can be combined with other low-frequency modulation.

SJ adjustable from 0 to levels greater than or equal to range in table. See Additional Stress Options (next) for more SJ capabilities.

Additional stress options

Phase Modulation Range with Option XSSC.


Maximum SSC Modulation with Option XSSC.

Enhanced spread spectrum clock option (Option STR and/or Option XSSC)

Characteristic	Description
Adds a modulator directly to the synthesizer clock output – modulation affects main and sub-rate clock output (regardless of the state of sub-rate output select), Data Output, and Trigger Output.
Modes	SSC or Phase Modulation (sinusoidal)
Data Rate Range	Full range of BERTScope
SSC Wave Shape	Triangle or Sine
SSC Frequency Range	20 kHz to 40 kHz
SSC Modulation Range	12,500 ppm at 6 Gb/s 6,200 ppm at 12 Gb/s 6,000 ppm at 12.5 Gb/s and above See Maximum SSC Modulation graph for range at lower clock rates
SSC Modulation Resolution	1 ppm
SSC Modulation Type	Down Spread, Center Spread, Up Spread
PM Frequency Range	10 Hz - 160 kHz
PM Frequency Resolution	1 Hz

 

PM modulation range – for modulation frequency 10 Hz - 2 kHz

Data rate	Maximum modulation
>6 Gb/s	6000 UI
3 to 6 Gb/s	3000 UI
1.5 to 3 Gb/s	1500 UI
0.75 to 1.5 Gb/s	750 UI
375 to 750 Mb/s	375 UI
187 to 375 Mb/s	187.5 UI
100 to 187 Mb/s	93.75 UI
Reduced for modulation frequencies >2 kHz. See Phase Modulation Range graph.

 

F/2 jitter generation option (Option F2, also requires Option STR)

Characteristic	Description
F/2 or sub-rate jitter is found in high data rate systems which multiplex up 2 or more lower data rate streams. The jitter results for lack of symmetry in the multiplexing clock, giving all of the even bits different pulse width than the odd bits. Unlike conventional DCD, F/2 jitter is independent of the logic state of the bit. F/2 jitter is part of the stress recipe used in testing compliance to some of the newer standards such as 802.3ap (10 Gb backplane Ethernet).
Supported Data Rates	8.0 and 10.3125 Gb/s
Modulation Range	0-5.0% UI

Extended stress generation option (Option PCISTR)

Characteristic	Description
This option adds additional stress generators required for compliance testing receivers to PCIe 2.0 specifications, internal to the BERTScope.
Clock Frequency Range	Up to 11.2 Gb/s
LFRJ Modulation Range	0-1.1 ns*5
LFRJ Frequency Range	Band-limited to 10 kHz - 1.5 MHz, with roll off to PCIe 2.0 specifications
LFSJ Modulation Range	0-368 ps*5 at 5 Gb/s
LFSJ Frequency Range	1-100 kHz

*⁵ Can be combined with other low-frequency modulation.

Characteristic	Description
The Extended Stress option also adds selectable bandwidth-limiting to the normal, broadband RJ generator.
RJ Frequency, Normal Mode	Band-limited to 10 MHz - 1 GHz
RJ Frequency, PCIE Mode	Band-limited to 1.5-100 MHz with roll off to PCIe 2.0 specifications

 

Error Detector

Clock and data inputs

Clock input

Characteristic	Description
Configuration	Single ended
Frequency Range
BSA85C	0.1 to 8.5 Gb/s
BSA125C	0.1 to 12.5 Gb/s
BSA175C	0.5 to 17.5 Gb/s*6
BSA260C	1 to 26 Gb/s*6
BSA286C	1 to 28.6 Gb/s*7

*⁶ A full- or half-rate clock may be used for data rates above 11.2 Gb/s.

*⁷ From 26 to 28.6 Gb/s the input detector operates at half rate (using even or odd bits).

Data and clock interfaces

Characteristic	Description
Connector	APC-3.5 Planar Crown®
Impedance	50 Ω
Threshold Voltage	–2 to +3.5 V
Threshold Presets	LVPECL, LVDS, LVTTL, CML, ECL, SCFL
Terminations	Variable, –2 V to +3 V Presets: +1.5, +1.3, +1, 0, –2 V, AC coupled
Max Nondistructible Input	–3 Vpeak, +4 Vpeak, applied to any connector

 

Clock/data delay

Characteristic	Description
Range	(Greater than 1 bit period in all cases)
Up to 1.1 GHz	30 ns
Above 1.1 GHz	3 ns
Resolution	100 fs
Self Calibration	Supported – At time of measurement, when temperature or bit rate are changed, instrument will recommend a self calibration. Operation takes less than 10 seconds

 

Data inputs

Characteristic	Description
Date Rate Range
BSA85C	0.1 to 8.5 Gb/s
BSA125C	0.1 to 12.5 Gb/s
BSA175C	0.5 to 17.5 Gb/s
BSA260C	1 to 26 Gb/s
BSA286C	1 to 28.6 Gb/s
Configuration	Differential
Format	NRZ
Polarity	Normal or Inverted
Threshold Alignment	Can auto-align to differential crossing point
Sensitivity
Single ended	100 mVp-p (typical)
Differential	50 mVp-p (typical)
Maximum input signal swing	2 Vp-p
Intrinsic Transition Time	16 ps typical, 10/90%, single ended (equivalent to >20 GHz detector bandwidth). Measured at input, ECL levels
Patterns
Hardware patterns	Industry-standard Pseudo-random (PRBS) of the following types: 2n – 1 where n = 7, 11, 15, 20, 23, 31
RAM patterns
User defined	128 bits to 128 Mb, 128-bit increments
Library	Wide variety including SONET/SDH, Fibre Channel based such as k28.5, CJTPAT; 2n patterns where n = 3, 4, 5, 6, 7, 9; Mark Density patterns for 2n where n = 7, 9, 23; and many more
RAM Pattern Capture	Capture incoming data up to 128 Mb in length. Edit captured data, send to Pattern Generator, Error Detector, or both
Capture modes
Capture by length	1 to 1,048,576 words. 1-word default. Words 128 bit in length
Capture by triggers	Captures when “Detector Start” on rear panel goes high, to maximum allowable length or until input goes low
Capture by length from trigger	Capture by length initiated from “Detector Start” input, to pre-specified length
Synchronization
Auto-resync	User-specified number of 128 bit words containing 1 or more errors per word initiates a re-sync attempt
Manual	User initiates re-sync
Pattern matching
Grab ‘n’ Go	Error Detector captures specified pattern length and compares next instances to find match (Fast method, but susceptible to ignoring logical errors)
Shift-to-Sync	Error Detector compares incoming pattern with reference RAM pattern, looks for match, if none found shifts pattern by one bit and compares again (Slower but most accurate method)
Error Detector Basic Measurements	BER, Bits Received, Re-syncs, Measured Pattern Generator and Error Detector Clock Frequencies

 

Error Detector ancillary connections

Front-panel Error Detector connections

Error correlation marker input (error analysis)

Characteristic	Description
Allows an external signal to provide a time-tagged marker to be placed in the error data set.
Logic Family	LVTTL (<0.5 V Low, >2.5 V High)
Threshold	+1.2 V
Minimum Pulse Width	128 clock periods
Maximum Repetition Rate	512 serial clock periods
Maximum Frequency	<4000 markers/s recommended
Interface	BNC female, >1 kΩ impedance into 0 V

 

BERTScope Burst Analysis Timing – BERTScope word size is 128 bits. An example timing diagram is shown here for a PRBS payload. Counting of bits will not start until a 128-bit word boundary occurs, meaning that after the blanking pulse transitions, up to 127 bits may pass before synchronization begins. For a PRBS, synchronization typically takes 5 words, or 640 bits. Similarly, bit measurement will continue for up to 127 bits after the blanking signal transitions again. RAM-based patterns take longer to synchronize.

Blank input

Characteristic	Description
Useful for recirculating loop fiber experiments or during channel training sequences. Causes errors to be ignored when active. Bit count, error count, and BER not counted. No re-sync occurs when counting is re-enabled.
Logic Family	LVTTL (<0.5 V Low, >2.5 V High)
Threshold	+1.2 V
Minimum Pulse Width	128 clock periods
Maximum Repetition Rate	512 serial clock periods
Interface	BNC female, >1 kΩ impedance into 0 V

 

Error output

Characteristic	Description
Provides a pulse when an error is detected. Useful for triggering an alarm while doing long-term monitoring, etc.
Minimum Pulse Width	128 clock periods
Transition Time	<500 ps
Output Levels	1000 mV nominal (0 V to 1 V low-high)
Interface	SMA female

 

Trigger output

Characteristic	Description
Provides a pulse trigger to external test equipment. It has two modes: 1. Divided Clock Mode: Pulses at 1/256th of the clock rate. 2. Pattern Mode: Pulse at a programmable position in the pattern (PRBS), or fixed location (RAM patterns).
Minimum Pulse Width	128 clock periods (Mode 1) 512 clock periods (Mode 2)
Transition Time	<500 ps
Output Levels	>300 mV amplitude, 650 mV offset
Interface	50 Ω SMA female

 

Rear-panel Error Detector connections

Detector start input

Characteristic	Description
Used to trigger the acquisition of incoming data into the Error Detector reference pattern memory. High level starts capture.
Amplitude	LVTTL (<0.5 V Low, >2.5 V High)
Threshold	+1.2 V
Minimum Pulse Width	128 serial clock periods
Maximum Repetition Rate	512 serial clock periods
Interface	SMA female, >1 kΩ impedance into 0 V

User interfaces

Taking usability to new heights

UI Setup Screens

• Easy navigation
• Logical layout and operation
• Multiple ways of moving between screens
• Relevant information right where you need it
• Color coding to alert you to the presence of nonstandard conditions

Editor screen

Editor Screen

• Used for pattern editing of standard and AB Page Select patterns, also mask editing
• Views in Binary, Decimal, or Hexadecimal
• Support for variable assignments, repeat loops, seeding of PRBS patterns
• Capture and editing of incoming data – for example, to make a repeating pattern out of real-world traffic
• Capture is available by trigger, by length, or by length following a trigger
• Capture is by number or words, 1 word is 128 bits. For example, a PRBS-7 (127 bits long) would be captured as 127 words, and would have overall length of 16,256 bits

BERTScope built-in parametric measurements

All BERTScopes come with eye diagrams and mask test capabilities as standard, along with error analysis.

Eye diagram

• 280×350 pixel waveform display
• Deep acquisition
• Automatic Measurements include:
• Rise Time
• Fall Time
• Unit Interval (Data, and also Clock)
• Eye Amplitude
• Noise Level of 1 or 0
• Eye Width
• Eye Height
• Eye Jitter (p-p and RMS)
• 0 Level, 1 Level
• Extinction Ratio
• Vertical Eye Closure Penalty (VECP)
• Dark Calibration
• Signal-to-Noise Ratio
• V_p-p, V_max, V_min, Crossing Levels
• Rising and Falling Crossing Level (picoseconds)
• Overshoot 0 Level and 1 Level
• Average Voltage/Power
• Cross Amplitude, Noise Level 1 or 0, Voltage
• Optical Modulation Amplitude (OMA)
• Sample Count
• Offset Voltage
• De-emphasis Ratio

Mask testing

• Library of standard masks (e.g. XFP, or edit custom masks)
• Addition of positive or negative mask margin
• Import of measured BER Contour to become process control mask
• At least 1000x the sample depth of traditional sampling oscilloscope masks is ideal for ensuring the absence of rare event phenomena

Optical units

An external optical receiver may be added to the input of the BERTScope detector. Through the user interface it is easy to input and save the characteristics of the receiver. Once accomplished, relevant units on physical layer displays are changed to optical power in dBm, μW, or mW. Coupling may be AC or DC, and the software steps the user through dark calibration.

For electrical signals, attenuation values can be entered to properly scale eye diagrams and measurements when external attenuators are used.

Variable-depth eye and mask Ttesting

For eye diagrams and mask testing, the depth of test may be varied in manual mode; the instrument will take the specified number of waveforms then stop. The range is 2,000 to 1,000,000 bits (complete waveforms). Alternatively, the default mode is Continuous, and the eye or mask test increases in depth over time.

Physical layer test option

BER contour testing

• Executed with same acquisition circuitry as eye diagram measurements for maximum correlation
• As-needed delay calibration for accurate points
• Automatic scaling, one-button measurement
• Extrapolates contours from measured data, increasing measurement depth with run time and repeatedly updating curve fits
• Easy export of fitted data in CSV format
• Contours available from 10^–6 to 10^–16 in decade steps

Basic jitter measurements

• Testing to T11.2 MJSQ BERTScan methodology (also called ‘Bathtub Jitter’)
• Deep measurements for quick and accurate extrapolation of Total Jitter at user-specified level, or direct measurement
• Separation of Random and Deterministic components, as defined in MJSQ
• As-needed delay calibration for accurate points
• Easy export of points in CSV format
• Easy one-button measurement
• User-specified amplitude threshold level, or automatic selection
• Selectable starting BER to increase accuracy when using long patterns, as defined in MJSQ

Q-factor measurement

• One-button measurement of a vertical cross section through the middle of the eye
• Easy visualization of system noise effects
• Export of data in CSV format

Compliance contour

• Validation of transmitter eye performance to standards such as XFP/XFI and OIF CEI
• Overlay compliance masks onto measured BER contours and easily see whether devices pass the BER performance level specified

Live data analysis option

The Live Data option is designed to measure parametric performance of traffic that is either unknown or non-repeating. This can include traffic with idle bits inserted such as in systems with clock rate matching. It is also suitable for probing line cards, etc.

The option uses one of the two front-end decision circuits to decide whether each bit is a one or zero by placing it in the center of the eye. The other is then used to probe the periphery of the eye to judge parametric performance. This method is powerful for physical layer problems, but will not identify logical problems due to protocol issues, where a zero was sent when it was intended to be a one.

Live data measurements can be made using BER Contour, Jitter Peak, Jitter Map, and Q-factor. Eye diagram measurements can be made on live data without the use of this option, providing a synchronous clock is available.

The Live Data Analysis option requires the Physical Layer Test option and must be used with a full-rate clock.

PatternVu equalization processing option

PatternVu*⁸ adds several powerful processing functions to the BERTScope:

CleanEye is an eye diagram display mode, which averages waveform data to present an eye diagram with the non-data-dependent jitter removed. This allows the user to view and measure data-dependent jitter such as Inter-Symbol Inference, giving an intuitive idea of the compensatable jitter present, for example. It is effective on any repeating pattern up to 32,768 bits long.

Single value waveform export is a utility which converts the CleanEye output to an export file in Comma Separated Vector (CSV) format. The output file, of up to 10⁵ bit points, can then be imported into Microsoft Excel or software analysis and simulation tools such as Stateye or MATLAB^®. This allows offline filtering of real captured data and the implementation of standards-based processing such as Transmitter Waveform Dispersion Penalty (TWDP) required by 802.3aq, the recent Long Reach MultiMode (LRM) 10 Gb Ethernet standard.

The FIR filter equalization processor allows the emulation of the communication channel to view and measure the eye as the detector in the receiver would, by applying a software linear filter to the data before it is displayed. For example, the FIR Filter can be used to emulate the lossy effects of a backplane channel, or alternatively, emulate the receiver’s equalization filter, facilitating the design and characterization of receiver-side equalization.

The filter characteristics are controlled by entering the individual weighting coefficients of a series of taps in the FIR filter. Up to 32 taps with tap spacing from 0.1 to 1.0 unit intervals (UI) can be programmed to allow fine resolution of the filter shape. The FIR Filter can be applied to repeating patterns up to 32,768 bits long.

Single edge jitter measurement allows truly deep BER-based jitter measurements to be applied to individual data edges at data rates above 3 Gb/s. The Single Edge Jitter Peak measurement function enables computation of jitter on a user-selectable single edge in the pattern, for repeating patterns up to 32,768 bits long. The resulting jitter measurement excludes data-dependent effects, showing only the uncorrelated jitter components such as Random Jitter (RJ), Bounded Uncorrelated Jitter (BUJ), and Periodic Jitter (PJ).

Flexible measurements enables users to specify exactly the portion of the CleanEye waveform to use for accurate measurement of amplitude, rise and fall time, and de-emphasis ratio. Preprogrammed formulas for standards such as PCI Express and USB 3.0 are included.

*⁸ PatternVu operates at data rates of 900 Mb/s and higher.

Error analysis

Error analysis is a powerful series of views that associate error occurrences so that underlying patterns can be easily seen. It is easy to focus in on a particular part of an eye diagram, move the sampling point of the BERTScope there, and then probe the pattern sensitivity occurring at that precise location. For example, it is straightforward to examine which patterns are responsible for late or early edges.

Many views come standard with the BERTScope Family.

Analysis views

Error Statistics view showing link performance in terms of bit and burst occurrences.


Strip Chart view showing bit and burst error performance over time. This can useful while temperature cycling as part of troubleshooting, for example.


The Pattern Sensitivity view is a powerful way of examining whether error events are pattern related. It shows which pattern sequences are the most problematic, and operates on PRBS and user-defined patterns.

• Error statistics: A tabular display of bit and burst error counts and rates
• Strip chart: A strip chart graph of bit and burst error rates
• Burst length: A histogram of the number of occurrences of errors of different lengths
• Error free interval: A histogram of the number of occurrences of different error-free intervals
• Correlation: A histogram showing how error locations correlate to user-set block sizes or external marker signal inputs
• Pattern sensitivity: A histogram of the number of errors at each position of the bit sequence used as the test pattern
• Block errors: A histogram showing the number of occurrences of data intervals (of a user-set block size) with varying numbers of errors in them

Error location capture

Characteristic	Description
Live Analysis	Continuous
Error Logging Capacity	Max. 2 GB file size
Error Events/Second	10,000
Maximum Burst Length	32 kb

 

Error analysis options

Forward error correction emulation

Because of the patented error location ability of the BERTScope, it knows exactly where each error occurs during a test. By emulating the memory blocks typical of block error correcting codes such as Reed-Solomon architectures, bit error rate data from uncorrected data channels can be passed through hypothetical error correctors to find out what a proposed FEC approach would yield. Users can set up error correction strengths, interleave depths, and erasure capabilities to match popular hardware correction architectures.

2-D error mapping

This analysis creates a two-dimensional image of error locations from errors found during the test. Error mapping based on packet size or multiplexer width can show if errors are more prone to particular locations in the packet or particular bits in the parallel bus connected to the multiplexer. This visual tool allows for human eye correlation, which can often illuminate error correlations that are otherwise very difficult to find – even with all the other error analysis techniques.

Jitter tolerance template option

Many standards call for SJ to be stepped through a template with different SJ amplitudes at particular modulation frequencies. This is easy with the built-in Jitter Tolerance function which automatically steps through a template that you designed, or one of the many standard templates in the library.

Standard library of templates

• 10GBASE LX4 802.3ae 3.125 Gb/s
• 10 GbE 802.3ae 10.3125 Gb/s
• 40 GbE 802.3ba LR4 10.3125 Gb/s
• 100 GbE 802.3ba LR4/ER4 25.78125 Gb/s
• CEI 11G Datacom Rx Ingress (D) 11 Gb/s
• CGE Telecom Rx Egress (Re) 11 Gb/s*⁹
• CEI 11G Telecom Rx Ingress (Ri) 11 Gb/s*⁹
• CEI 11G Total Wander 11.1 Gb/s
• CEI 11G Total Wander 9.95 Gb/s
• CEI 6G Total Wander 4.976 Gb/s
• CEI 6G Total Wander 6.375 Gb/s
• CEI 25G Total Wander 25.78125 Gb/s
• FBB DIMM1 3.2 Gb/s
• FBB DIMM1 4.0 Gb/s
• FBB DIMM1 4.8 Gb/s
• FBB DIMM2 3.2 Gb/s
• FBB DIMM2 4.0 Gb/s
• FBB DIMM2 4.8 Gb/s
• Fibre Channel 1.0625 Gb/s
• Fibre Channel 2.125 Gb/s
• Fibre Channel 4.25 Gb/s
• Fibre Channel 8G 8.5 Gb/s
• Fibre Channel 16G 14.025 Gb/s
• OTN OTU-1 2.666G*⁹
• OTN OTU-2 10.709 Gb/s
• OTN(10BASE-R) 11.1 Gb/s
• SAS (SCSI) 1.5 Gb/s
• SAS (SCSI) 3 Gb/s
• SDH 0.172 STM-1 155M*⁹
• SDH 0.172 STM-16 2.4832 Gb/s*⁹
• SDH 0.172 STM-4 622 Mb/s*⁹
• SDH 0.172 STM-64 9.956 Gb/s*⁹
• SDH STM-16 2.48832 Gb/s*⁹
• SDH STM-64 9.9532 Gb/s*⁹
• SONET OC-48 2.48832 Gb/s*⁹
• SONET OC12 622 Mb/s*⁹
• SONET OC192 9.9532 Gb/s*⁹
• SONET OC192 9.95 Gb/s*⁹
• SONET OC3 155 Mb/s*⁹
• SONET OC48 2.4832 Gb/s*⁹
• USB 3.0 5 Gb/s
• XAUI 3.125 Gb/s
• XFI ASIC Rx In Datacom (D) 10.3125 Gb/s
• XFI ASIC Rx In Datacom (D) 10.519 Gb/s
• XFI ASIC Rx In Telecom (D) 10.70 Gb/s
• XFI ASIC Rx In Telecom (D) 9.95328 Gb/s*⁹
• XFI Host Rx In Datacom (C) 10.3125 Gb/s
• XFI Host Rx In Datacom (C) 10.519 Gb/s
• XFI Host Rx In Telecom (C) 10.70 Gb/s*⁹
• XFI Host Rx In Telecom (C) 9.95328 Gb/s*⁹
• XFI Module Tx In Datacom (B') 10.3125 Gb/s
• XFI Module Tx In Datacom (B') 10.519 Gb/s
• XFI Module Tx In Telecom (B') 10.70 Gb/s*⁹
• XFI Module Tx In Telecom (B') 9.95328 Gb/s*⁹

Some of the areas of adjustment include:

• BER confidence level
• Test duration per point
• BER threshold
• Test device relaxation time
• Imposition of percentage margin onto template
• Test precision
• Control over A/B Pattern switch behavior

Also included is the ability to test beyond the template to device failure at each chosen point, and the ability to export data either as screen images or CSV files.

*⁹ Requires Option XSSC.

Jitter map option

Automated jitter decomposition with long pattern jitter triangulation

Jitter Map*¹⁰ extends BER-based jitter decomposition beyond Dual Dirac measurement of Total Jitter (TJ), Random Jitter (RJ), and Deterministic Jitter (DJ) to a comprehensive set of subcomponents. It can also measure and decompose jitter on extremely long patterns, such as PRBS-31, providing that it can first run on a shorter synchronized data pattern.

Features include:

• DJ breakdown into Bounded Uncorrelated Jitter (BUJ), Data Dependent Jitter (DDJ), Inter-Symbol Interference (ISI), Duty Cycle Distortion (DCD), and Sub-Rate Jitter (SRJ)*¹¹ including F/2 (or F2) Jitter
• BER based for direct (non-extrapolated) Total Jitter (TJ) measurement to 10^–12 BER and beyond
• Separation of correlated and uncorrelated jitter components eliminates mistaking long pattern DDJ for RJ
• Visualization of RJ RMS measured on individual edges of the data pattern
• J2 and J9 jitter measurements for 100 GbE applications
• Additional levels of breakdown not available from other instruments such as: Emphasis Jitter (EJ), Uncorrelated Jitter (UJ), Data Dependent Pulse Width Shrinkage (DDPWS), and Non-ISI
• Intuitive, easy-to-navigate jitter tree

*¹⁰ Jitter Map operates at data rates of 900 Mb/s and higher.

*¹¹ SRJ and F/2 Jitter operate up to 8.5 Gb/s (BSA85C), 11.2 Gb/s (BSA125C, BSA175C, BSA260C, BSA286C).

Stressed live data option

The BERTScope Stressed Live Data software option enables engineers to add various types of stress to real data traffic in order to stress devices with bit sequences representative of the environment they will encounter once deployed. Using live traffic with added stress tests the boundaries of device performance and lends added confidence to designs before they are shipped.

• Full range of calibrated stress available on the BERTScope, including Sinusoidal Jitter (SJ), Random Jitter (RJ), Bounded Uncorrelated Jitter (BUJ), Sinusoidal Interference (SI), F/2 Jitter, and Spread Spectrum Clocking (SSC)
• Data rate support up to the maximum of the BERTScope
• Full-rate clock required up to 11.2 Gb/s, half-rate clock required above 11.2 Gb/s

Symbol filtering option

Symbol filtering enables asynchronous BER testing, including Jitter Tolerance testing, on incoming data streams that have a nondeterministic number of clock compensation symbols inserted into the bit stream, as is common in 8b/10b encoded systems when placed in loopback for receiver testing.

• Supports asynchronous receiver testing for USB 3.0, SATA, and PCI Express
• User-specified symbols are automatically filtered from the incoming data to maintain synchronization
• The Error Detector maintains a count of filtered bits for accurate BER measurement
• Operates at data rates up to 11.2 Gb/s

General

PC related

Characteristic	Description
Display	TFT touch screen 640×480 VGA
Touch Sensor	Analog resistive
Processor	Pentium® P4 1.5 GHz or greater
Hard Disk	40 GB or greater
DRAM	1 GB
Operating System	Windows XP Professional
Remote Control Interfaces	IEEE-488 (GPIB) or TCP/IP

 

Supported interfaces

• DVI/VGA display
• USB 2.0 (6 total, 2 front, 4 rear)
• 100BASE-T Ethernet LAN
• IEEE-488 (GPIB)
• Serial RS-232

 

Physical

Dimension	mm	in.
Height	220	8.75
Width	394	15.5
Depth	520	20.375
Weight	kg	lb.
Instrument Only	25	55
Shipping	34.5	76
Other
Power	460 W
Voltage	100 to 240 VAC (±10%), 50 to 60 Hz

 

Environmental

Characteristic	Description
Warm-up Time	20 minutes
Operating Temperature Range	10 to 35 °C
Operating Humidity	Noncondensing at 35 °C, 15 to 65%
Certifications	EU EMC Directive (CE-Marked) LVD Low Voltage Directive US Listed UL61010-1 Canada Certified CAN/CSA 61010-1

 

Support

Characteristic	Description
Period	1 year (extendable to 3 years with orderable option)
Calibration Interval	1 year