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BERTScope Bit Error Rate Tester
The Confidence of a BERT with the Insight of an Oscilloscope
The BERTScope™ Bit Error Rate Tester Series provides a new approach to signal integrity measurements of serial data systems. Perform bit error ratio detection more quickly, accurately, and thoroughly by bridging eye diagram analysis with BER pattern generation. The BERTScope™ Bit Error Rate Tester Series enables you to easily isolate problematic bit and pattern sequences, then analyze further with seven types of advanced error analysis that deliver unprecedented statistical measurement depth.
Models in the BERTScope Bit Error Rate Tester Series:
| Model | Description | Max Bit Rate | List Price | Shop Online or Get a Quote |
|---|---|---|---|---|
|
BSA85CPG Read Reviews Write Review |
Pattern Generator | 8.5 Gb/s | $94,800 | Configure |
|
BSA85C Read Reviews Write Review |
Bit Error Ratio Analyzer | 8.5 Gb/s | $129,000 | Configure |
|
BSA125CPG Read Reviews Write Review |
Pattern Generator | 12.5 Gb/s | $140,000 | Configure |
|
BSA175CPG Read Reviews Write Review |
Pattern Generator | 17.5 Gb/s | $165,000 | Configure |
|
BSA125C Read Reviews Write Review |
Bit Error Ratio Analyzer | 12.5 Gb/s | $186,000 | Configure |
|
BSA175C Read Reviews Write Review |
Bit Error Ratio Analyzer | 17.5 Gb/s | $210,000 | Configure |
|
BSA260CPG Read Reviews Write Review |
Pattern Generator | 26.0 Gb/s | $239,000 | Configure |
|
BSA260C Read Reviews Write Review |
Bit Error Ratio Analyzer | 26.0 Gb/s | $284,000 | Configure |
Features | Benefits |
| Pattern Generation and Error Analysis, highspeed BER Measurements up to 26 Gb/s | The combination of generation and analysis in one instrument enables receiver BER compliance testing for today's 2nd and 3rd Generation Serial Standards |
| Integrated Stress Generator for stressed eye sensitivity (SRS) and jitter tolerance compliance testing | A test signal's data rate, applied stress, and data pattern can be changed on the fly, independent of each other; enabling a diverse set of signal variations for testing chipset/system sensitivity. |
| Integrated, BER correlated eye diagram analysis with pass/fail masks for PCI Express, USB, SATA and other serial standards | Enhances the debug experience unlike other BERT's by providing a familiar eye diagram of the test results to compare against a standards specific mask. |
| Error Location and BER contour analysis on PRBS and other digital signals up to 26 GB/sec. | Provides a quick understanding of signal integrity in terms of BER. Error location provides detailed BER pattern sensitivities to speed up identification of deterministic vs. random BER errors |
| Optional Jitter Map provides fast jitter decomposition, accurate stress calibration at the DUT input. | Fast, effective method for determining long pattern PRBS31 jitter composition with triangulation. Graphical representation makes jitter analysis more thorough, yet simpler to follow. |
| Optional Digital Pre-emphasis Processor provides user controlled pre-emphasis on pattern generator supplied data. | Enables testing with compliant signals for standards like PCI Express, 10GBASE-KR, SATA, 40GBASE-KR4, 100GBASE-CAUI |
| Optional Clock Recovery Units provide clock recovery up to 28.6 Gb/s | Enables compliant testing and accurate Eye Pattern Analysis for high-speed serial and communication system standards. |
| Application | |
|---|---|
USB 3.0 Receiver Compliance TestingAll aspects of USB 3.0 receiver testing are covered, including stressed eye calibration and jitter tolerance testing with measured device margin. |
USB |
Six Sigma’ Mask Testing with a BERTScope® Bit Error Rate TesterUsing Six Sigma for citical insight. |
Jitter Measurement and Timing Analysis |
Stressed Eye: “Know What You’re Really Testing With”Using BER-based analysis to improve stress calibration measurements. |
Jitter Measurement and Timing Analysis |
BERTScope® Bit Error Rate Testers Jitter Map “Under the Hood”A New Methodology for Jitter Separation |
Jitter Measurement and Timing Analysis |
Comparing Jitter Using a BERTScope® Bit Error Rate TestingComparison of DCD and F/2 Jitter. |
Jitter Measurement and Timing Analysis |
Evaluating Stress Components using BER-Based Jitter MeasurementsSelf-verified jitter measurements using a BER-based Jitter Peak measurement. |
Jitter Measurement and Timing Analysis |
Bridging the Gap Between BER and Eye Diagrams — A BER Contour TutorialIntroduction to the BER Contour measurement. |
Jitter Measurement and Timing Analysis |
PCI Express® Transmitter PLL Testing — A Comparison of MethodsOverview of significant methods for performing PLL Testing |
Jitter Measurement and Timing Analysis |
BERTScope Content ArchiveRequest copies of historical content from SyntheSys Research (now Tektronix Inc.) related to BERTScope. |
|
Characterizing an SFP+ Transceiver at the 16G Fibre Channel RateMeasurements needed to test an SFP+ transceiver to the 16G Fibre Channel standard. |
Jitter Measurement and Timing Analysis |
| Application | |
|---|---|
PCI Express 3.0 - Physical Layer TestingThis webinar will provide you with important information to speed up physical layer compliance testing for PCI Express 3.0 Serial Bus designs and systems. Learn how to setup and perform transmitter and receiver testing required by the PCI-SIG during this webinar |
PCI Express |
Verification and Compliance Testing of 10Gb/sec Thunderbolt DesignsLearn about the Thunderbotl technology, tests and challenges, and how Tektronix supports this emerging technology |
|
Receiver Testing to Third Generation Standards WebinarWith the advent of 3rd Generation Serial Standards at rates above 5 GT/sec, it is critically important to characterize receiver performance for a successful serial communication system design. This seminar, using PCI Express 3.0 and USB3 as example standards, will highlight the latest trends and illustrate important practical learnings for successful test execution. |
Serial Communications |
How to Choose the Right Platform for Jitter MeasurementsLearn what to consider when selecting a platform for jitter measurements. |
Jitter Measurement and Timing Analysis |
Beyond Receiver Interoperability Testing WebinarThis 45 minute, live webinar will focus on the latest tools and techniques for properly performing jitter tolerance and stressed receiver sensitivity testing - including characterization and margin testing of next generation receivers. . |
Storage |
RELATED INFORMATION
Get your FREE Eye Diagram and Clock Recovery Posters
These posters are about testing digital high speed communications electronics, and are intended for electronics engineers who work to verify compliance of their products.
Download Anatomy of an Eye Diagram App Note
Discusses different ways that information from an eye diagram can be sliced to gain more insight. It also discusses some basic ways that transmitters, channels, and receivers are tested.
Solving Serial Data Test Complexity for PCI Express 3.0
Learn more about our automated test suite for the PCI-SIG BASE and CEM specification compliance tests for PCI Express 3.0!
Get your NEW Product Catalogs now!
Three short form Tektronix catalogs are available - Test and Measurement, Bench Products and Video Test.
Other Products to Consider
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