RapidIO®
RapidIO architecture delivers significantly increased transmission speeds to enable the design of next-generation networking and communications equipment. Debugging RapidIO designs for compliance requires accurate jitter analysis including Rj determination with 2nd order PLL clock recovery capability. Tektronix DSA70000B with DPOJET Jitter Analysis toolset and Serial Triggering enables engineers implementing RapidIO into their designs to identify and resolve these issues quickly and efficiently.
Webinars
View All Serial Data Webinars
These webinars will cover serial data fundamentals including clock recovery, jitter analysis and compliance testing. Additional advanced topics include receiver testing and equalization.
Application Notes
Understanding and Performing RapidIO Testing
This application note describes measurements that engineers must consider to quickly and efficiently implement RapidIO into their designs.RapidIO Architecture: Building the Next-Generation Networking Infrastructure
Technical Brief describing RapidIO, a high-performance, packet-switched bus technology, that delivers the bandwidth, software independence, fault tolerance and low latency needed for the design of next-generation networking equipment in the communications market.Customer Case Study: Tundra Semiconductor
Read about how the Tektronix TLA Series logic analyzers enabled Tundra to save significant time and effort in the verification and debug phases of RapidIO switch development to get to market faster.- View All
