Download Part 1 - FPGA
With Part One you receive a 25 minute audio visual webinar, a downloadable presentation with speaker notes, and a companion application note, "Simplifying Xilinx and Altera FPGA Debug," that explain:

• How choosing the right FPGA debug methodology can reduce debug and validation time
• The advantages and disadvantages of test equipment alternates
• How to take advantage of easier to use and less intrusive FPGA debug methodologies

Webinar Presenter

Bruce Ableidinger, Director of Business Development, First Silicon Solutions
First Silicon Solutions (FS2) specializes in hardware verification and debug technologies including OCI® (On-Chip Instrumentation) custom silicon IP, development tools, and design services for programming, testing and debug of embedded systems in FPGA, SoC, SOPC, ASSP and ASIC designs. Bruce's job responsibilities include technology tracking, strategic planning and new product definition. He has a BSEE from Washington State University and an MSCS from Oregon State University.

Download Part 2 - Memory
In Part Two you receive a 20 minute audio visual webinar, a downloadable presentation with speaker notes, and the technical article "Verify and Debug DDR2 Memory Systems."

Part Two covers mainstream memory technologies such as DDR SDRAMs as used in today's embedded systems and explains:

• How DDR2 SDRAMs as the next generation of memories will be used in future embedded designs
• How they are implemented using fast edges, high clock frequencies and low voltages that require careful verification and testing to ensure reliable memory system operation
• Effective ways to validate and to debug DDR and DDR2 memory in embedded systems designs

Webinar Presenter

David Haworth, Logic Analyzer Memory and Computer Application Specialist, Tektronix, Inc.
Dave's expertise spans 27 years of memory application specialization, including DDR2, DDR3 and FB-DIMM standards. Dave was key in creating the VXI instrumentation bus standard, VXIbus Consortium, VXIplug&play System Alliance and SCPI Consortium. He served as the President of the VXIbus Consortium for eight years.

Download Part 4 - Low-Speed Serial
In Part Four, we look at key trends in the design of low-speed serial buses, including RS-232, I²C, SPI and CAN bus design in the consumer electronics, industrial controls and medical equipment industries. You receive a 25 minute audio-visual presentation, a downloadable presentation with speaker notes, and the application note "Debugging Low-speed Serial Buses in Embedded System Designs." Access Part Four and gain key insights on solving the design challenges of:

• Difficult event triggering
• Error-prone manual decoding
• Unconfirmed message transmission
• Limited total system invisibility

Webinar Presenter

Jerry Mark, Product Marketing Engineer, Tektronix, Inc.
Jerry has been in high technology for 27 years, 16 years with Tektronix in a variety of roles, including: field service, technical support, metrology engineering, and software applications design and development. Currently, he is actively involved in low-speed serial data technologies and customer applications. Jerry holds a bachelor's degree in Electrical Engineering from Portland State University.